diff options
| author | Ido Schimmel <idosch@mellanox.com> | 2015-07-29 23:33:48 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2015-07-30 00:05:00 -0700 |
| commit | 4ec14b7634b298186f18f65d959354dc3c60e02c (patch) | |
| tree | a84c854cdde90198542c2468f043b75b5dec83a8 /drivers/net/ethernet/mellanox/mlxsw/port.h | |
| parent | eda6500a987a027b78a275c11db6454404a626aa (diff) | |
| download | linux-stable-4ec14b7634b298186f18f65d959354dc3c60e02c.tar.gz linux-stable-4ec14b7634b298186f18f65d959354dc3c60e02c.tar.bz2 linux-stable-4ec14b7634b298186f18f65d959354dc3c60e02c.zip | |
mlxsw: Add interface to access registers and process events
Ethernet Management Datagrams (EMADs) are Ethernet packets sent between
the host and the device in order to configure the available device registers.
Another use case is notifications sent from the device to the host,
letting it know about certain events, such as port up / down.
Add the ability to construct EMADs with provisions to construct and
parse the registers' payloads. Implement EMAD transaction layer
which is responsible for the reliable transmission of EMADs. Also, add
an infrastructure used by the switch driver to register for particular
events generated by the device.
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Elad Raz <eladr@mellanox.com>
Reviewed-by: Scott Feldman <sfeldma@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/port.h')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/port.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/port.h b/drivers/net/ethernet/mellanox/mlxsw/port.h index 1b43c7d58ac5..4606966af980 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/port.h +++ b/drivers/net/ethernet/mellanox/mlxsw/port.h @@ -42,6 +42,12 @@ #define MLXSW_PORT_DEFAULT_VID 1 +#define MLXSW_PORT_SWID_DISABLED_PORT 255 +#define MLXSW_PORT_SWID_ALL_SWIDS 254 +#define MLXSW_PORT_SWID_TYPE_ETH 2 + +#define MLXSW_PORT_MID 0xd000 + #define MLXSW_PORT_MAX_PHY_PORTS 0x40 #define MLXSW_PORT_MAX_PORTS MLXSW_PORT_MAX_PHY_PORTS @@ -49,4 +55,17 @@ #define MLXSW_PORT_DONT_CARE (MLXSW_PORT_MAX_PORTS) +enum mlxsw_port_admin_status { + MLXSW_PORT_ADMIN_STATUS_UP = 1, + MLXSW_PORT_ADMIN_STATUS_DOWN = 2, + MLXSW_PORT_ADMIN_STATUS_UP_ONCE = 3, + MLXSW_PORT_ADMIN_STATUS_DISABLED = 4, +}; + +enum mlxsw_reg_pude_oper_status { + MLXSW_PORT_OPER_STATUS_UP = 1, + MLXSW_PORT_OPER_STATUS_DOWN = 2, + MLXSW_PORT_OPER_STATUS_FAILURE = 4, /* Can be set to up again. */ +}; + #endif /* _MLXSW_PORT_H */ |