diff options
| author | Daniel Machon <daniel.machon@microchip.com> | 2022-09-20 12:14:31 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-09-23 09:53:10 +0100 |
| commit | 211225428d65882ceccfbde49ab6f4d832badc0c (patch) | |
| tree | 7a7251eaa72e83a7d5003c320a9605be671780c7 /drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h | |
| parent | e02a5ac6bf7763edcd9590b98a14dd17f49a5248 (diff) | |
| download | linux-stable-211225428d65882ceccfbde49ab6f4d832badc0c.tar.gz linux-stable-211225428d65882ceccfbde49ab6f4d832badc0c.tar.bz2 linux-stable-211225428d65882ceccfbde49ab6f4d832badc0c.zip | |
net: microchip: sparx5: add support for offloading ets qdisc
Add support for offloading ets qdisc to sparx5 switch.
The ets qdisc makes it possible to configure a mix og strict and
bandwidth-sharing bands. The ets qdisc must be attached as a root qdisc.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h')
| -rw-r--r-- | drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h index 87a5b169c812..fa2eb70f487a 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h @@ -3098,6 +3098,21 @@ enum sparx5_target { #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) +/* HSCH:HSCH_DWRR:DWRR_ENTRY */ +#define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH, 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) + +#define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) +#define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ + FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x) +#define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\ + FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x) + +#define HSCH_DWRR_ENTRY_DWRR_BALANCE GENMASK(19, 0) +#define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\ + FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) +#define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ + FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) + /* HSCH:HSCH_MISC:HSCH_CFG_CFG */ #define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) |