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| author | Romain Gantois <romain.gantois@bootlin.com> | 2024-03-26 14:32:13 +0100 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-03-28 19:21:34 -0700 |
| commit | 0f671b3b6edf85cfe6fc80ad42963973bee1838c (patch) | |
| tree | d414f840c1c4f919b1ff1ebd91bc6dcd98325a93 /drivers/net/pcs/pcs-rzn1-miic.c | |
| parent | 30dc5873967ecc0282a8283622156cba4be8daf4 (diff) | |
| download | linux-stable-0f671b3b6edf85cfe6fc80ad42963973bee1838c.tar.gz linux-stable-0f671b3b6edf85cfe6fc80ad42963973bee1838c.tar.bz2 linux-stable-0f671b3b6edf85cfe6fc80ad42963973bee1838c.zip | |
net: pcs: rzn1-miic: Init RX clock early if MAC requires it
The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be
started before it initializes its own hardware, thus before it calls
phylink_start.
Implement the pcs_pre_init() callback so that the RX clock signal can be
enabled early if necessary.
Reported-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@bootlin.com/
Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/20240326-rxc_bugfix-v6-7-24a74e5c761f@bootlin.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/pcs/pcs-rzn1-miic.c')
| -rw-r--r-- | drivers/net/pcs/pcs-rzn1-miic.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index 4bd66fdde367..d0a722d43368 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -279,10 +279,38 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, return -EINVAL; } +static int miic_pre_init(struct phylink_pcs *pcs) +{ + struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); + struct miic *miic = miic_port->miic; + u32 val, mask; + + /* Start RX clock if required */ + if (pcs->rxc_always_on) { + /* In MII through mode, the clock signals will be driven by the + * external PHY, which might not be initialized yet. Set RMII + * as default mode to ensure that a reference clock signal is + * generated. + */ + miic_port->interface = PHY_INTERFACE_MODE_RMII; + + val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) | + FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS); + mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED; + + miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val); + + miic_converter_enable(miic, miic_port->port, 1); + } + + return 0; +} + static const struct phylink_pcs_ops miic_phylink_ops = { .pcs_validate = miic_validate, .pcs_config = miic_config, .pcs_link_up = miic_link_up, + .pcs_pre_init = miic_pre_init, }; struct phylink_pcs *miic_create(struct device *dev, struct device_node *np) |