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| author | Vivek Natarajan <vnatarajan@atheros.com> | 2010-04-05 14:48:04 +0530 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2010-04-07 14:37:57 -0400 |
| commit | 53bc7aa08b48e5cd745f986731cc7dc24eef2a9f (patch) | |
| tree | 5ddee6375615343ff30a63878ef4765b2cd2921c /drivers/net/wireless/ath/ath9k/phy.h | |
| parent | d5cdfacb35ed886271d1ccfffbded98d3447da17 (diff) | |
| download | linux-stable-53bc7aa08b48e5cd745f986731cc7dc24eef2a9f.tar.gz linux-stable-53bc7aa08b48e5cd745f986731cc7dc24eef2a9f.tar.bz2 linux-stable-53bc7aa08b48e5cd745f986731cc7dc24eef2a9f.zip | |
ath9k: Add support for newer AR9285 chipsets.
This patch adds support for a modified newer version of AR9285
chipsets.
Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/phy.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/phy.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h index 0999a495fd46..0132e4c9a9f9 100644 --- a/drivers/net/wireless/ath/ath9k/phy.h +++ b/drivers/net/wireless/ath/ath9k/phy.h @@ -503,6 +503,8 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah, #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 #define AR_PHY_TX_PWRCTRL7 0xa274 +#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 +#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 @@ -513,8 +515,16 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah, #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 #define AR_PHY_TX_GAIN_TBL1 0xa300 -#define AR_PHY_TX_GAIN 0x0007F000 -#define AR_PHY_TX_GAIN_S 12 +#define AR_PHY_TX_GAIN_CLC 0x0000001E +#define AR_PHY_TX_GAIN_CLC_S 1 +#define AR_PHY_TX_GAIN 0x0007F000 +#define AR_PHY_TX_GAIN_S 12 + +#define AR_PHY_CLC_TBL1 0xa35c +#define AR_PHY_CLC_I0 0x07ff0000 +#define AR_PHY_CLC_I0_S 16 +#define AR_PHY_CLC_Q0 0x0000ffd0 +#define AR_PHY_CLC_Q0_S 5 #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 |