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| author | Zong-Zhe Yang <kevin_yang@realtek.com> | 2023-01-13 17:06:31 +0800 |
|---|---|---|
| committer | Kalle Valo <kvalo@kernel.org> | 2023-01-16 15:38:12 +0200 |
| commit | 7f495de6ae7d31f098970fb45a038c9f69b1bf75 (patch) | |
| tree | 72960011256e490ca8f6cf574c817fc8c1a7a67f /drivers/net/wireless/realtek/rtw89/rtw8852ae.c | |
| parent | 3aa83062c3ec64dd757554a00653cc2d42179f12 (diff) | |
| download | linux-stable-7f495de6ae7d31f098970fb45a038c9f69b1bf75.tar.gz linux-stable-7f495de6ae7d31f098970fb45a038c9f69b1bf75.tar.bz2 linux-stable-7f495de6ae7d31f098970fb45a038c9f69b1bf75.zip | |
wifi: rtw89: fix assignation of TX BD RAM table
TX BD's RAM table describes how HW allocates usable buffer section
for each TX channel at fetch time. The total RAM size for TX BD is
chip-dependent. For 8852BE, it has only half size (32) for TX channels
of single band. Original table arrange total size (64) for dual band.
It will overflow on 8852BE circuit and cause section conflicts between
different TX channels.
So, we do the changes below.
* add another table for single band chip and export both kind of tables
* point to the expected one in rtw89_pci_info by chip
Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230113090632.60957-4-pkshih@realtek.com
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/rtw8852ae.c')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/rtw8852ae.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/rtw8852ae.c b/drivers/net/wireless/realtek/rtw89/rtw8852ae.c index 0cd8c0c44d19..d835a44a1d0d 100644 --- a/drivers/net/wireless/realtek/rtw89/rtw8852ae.c +++ b/drivers/net/wireless/realtek/rtw89/rtw8852ae.c @@ -44,6 +44,7 @@ static const struct rtw89_pci_info rtw8852a_pci_info = { .tx_dma_ch_mask = 0, .bd_idx_addr_low_power = NULL, .dma_addr_set = &rtw89_pci_ch_dma_addr_set, + .bd_ram_table = &rtw89_bd_ram_table_dual, .ltr_set = rtw89_pci_ltr_set, .fill_txaddr_info = rtw89_pci_fill_txaddr_info, |