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| author | Kamil Horák (2N) <kamilh@axis.com> | 2024-07-12 17:07:06 +0200 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-07-14 20:38:34 -0700 |
| commit | 2c1583290b08c5aa9005178a573be8f329de2976 (patch) | |
| tree | 74887925acff92be14b2f01ddf3b969a684a41fc /drivers/net | |
| parent | d944c27a9d58179b2fd96e23104f213481ec1e8d (diff) | |
| download | linux-stable-2c1583290b08c5aa9005178a573be8f329de2976.tar.gz linux-stable-2c1583290b08c5aa9005178a573be8f329de2976.tar.bz2 linux-stable-2c1583290b08c5aa9005178a573be8f329de2976.zip | |
net: phy: bcm54811: New link mode for BroadR-Reach
Introduce a new link mode necessary for 10 MBit single-pair
connection in BroadR-Reach mode on bcm5481x PHY by Broadcom.
This new link mode, 10baseT1BRR, is known as 1BR10 in the Broadcom
terminology. Another link mode to be used is 1BR100 and it is already
present as 100baseT1, because Broadcom's 1BR100 became 100baseT1
(IEEE 802.3bw).
Signed-off-by: Kamil Horák (2N) <kamilh@axis.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20240712150709.3134474-2-kamilh@axis.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/phy/phy-core.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index a235ea2264a7..1f98b6a96c15 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -13,7 +13,7 @@ */ const char *phy_speed_to_str(int speed) { - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102, + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 103, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n"); @@ -266,6 +266,7 @@ static const struct phy_setting settings[] = { PHY_SETTING( 10, FULL, 10baseT1S_Full ), PHY_SETTING( 10, HALF, 10baseT1S_Half ), PHY_SETTING( 10, HALF, 10baseT1S_P2MP_Half ), + PHY_SETTING( 10, FULL, 10baseT1BRR_Full ), }; #undef PHY_SETTING |