diff options
| author | Bruce Allan <bruce.w.allan@intel.com> | 2010-09-22 17:15:33 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-09-22 20:41:19 -0700 |
| commit | 87fb7410cd8d4396dee0155526568645adba3b99 (patch) | |
| tree | 7ee2e3c0cd3429eb98573f02c141d4011c3e1f8d /drivers/net | |
| parent | 8395ae8303255b31a8625035fc98391c88b0c257 (diff) | |
| download | linux-stable-87fb7410cd8d4396dee0155526568645adba3b99.tar.gz linux-stable-87fb7410cd8d4396dee0155526568645adba3b99.tar.bz2 linux-stable-87fb7410cd8d4396dee0155526568645adba3b99.zip | |
e1000e: 82579 SMBus address and LEDs incorrect after device reset
Since the hardware is prevented from performing automatic PHY configuration
(the driver does it instead), the OEM_WRITE_ENABLE bit in the EXTCNF_CTRL
register will not get cleared preventing the SMBus address and the LED
configuration to be written to the PHY registers. On 82579, do not check
the OEM_WRITE_ENABLE bit.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/e1000e/ich8lan.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 822de4830c67..fc8c3cef0526 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -990,9 +990,9 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; - if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && - ((hw->mac.type == e1000_pchlan) || - (hw->mac.type == e1000_pch2lan))) { + if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && + (hw->mac.type == e1000_pchlan)) || + (hw->mac.type == e1000_pch2lan)) { /* * HW configures the SMBus address and LEDs when the * OEM and LCD Write Enable bits are set in the NVM. |