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author | Alan Douglas <adouglas@cadence.com> | 2020-07-22 16:33:12 +0530 |
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committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-07-28 11:31:18 +0100 |
commit | 3ef5d16f50f8c32abd73e0c3bf4af690c9911cc7 (patch) | |
tree | 1715a6cf976a98345a3728eb192eeee08ff8ebb8 /drivers/pci/controller/cadence/pcie-cadence.h | |
parent | e3bca37d15dca118f2ef1f0a068bb6e07846ea20 (diff) | |
download | linux-stable-3ef5d16f50f8c32abd73e0c3bf4af690c9911cc7.tar.gz linux-stable-3ef5d16f50f8c32abd73e0c3bf4af690c9911cc7.tar.bz2 linux-stable-3ef5d16f50f8c32abd73e0c3bf4af690c9911cc7.zip |
PCI: cadence: Add MSI-X support to Endpoint driver
Implement ->set_msix() and ->get_msix() callback functions in order
to configure MSIX capability in the PCIe endpoint controller.
Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host.
cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual
address) from "struct cdns_pcie_epf" that gets initialized in
->set_bar() call back function.
[kishon@ti.com: Re-implement MSIX support in accordance with the
re-designed core MSI-X interfaces]
Link: https://lore.kernel.org/r/20200722110317.4744-11-kishon@ti.com
Signed-off-by: Alan Douglas <adouglas@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.h')
-rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 7c804ac1dbc2..dd910a1c30fb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -113,6 +113,7 @@ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 /* * Root Port Registers (PCI configuration space for the root port function) @@ -303,6 +304,14 @@ struct cdns_pcie_rc { }; /** + * struct cdns_pcie_epf - Structure to hold info about endpoint function + * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers + */ +struct cdns_pcie_epf { + struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS]; +}; + +/** * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver * @pcie: Cadence PCIe controller * @max_regions: maximum number of regions supported by hardware @@ -321,6 +330,7 @@ struct cdns_pcie_rc { * @lock: spin lock to disable interrupts while modifying PCIe controller * registers fields (RMW) accessible by both remote RC and EP to * minimize time between read and write + * @epf: Structure to hold info about endpoint function */ struct cdns_pcie_ep { struct cdns_pcie pcie; @@ -334,6 +344,7 @@ struct cdns_pcie_ep { u8 irq_pending; /* protect writing to PCI_STATUS while raising legacy interrupts */ spinlock_t lock; + struct cdns_pcie_epf *epf; }; |