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| author | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:02 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-28 13:31:02 -0500 |
| commit | fb3d102fc20b2f150fa9a0ba576cd44af79e3518 (patch) | |
| tree | 2ffdd4bd8a973409e76aa469a0691ba2c3cd39cd /drivers/pci/controller/dwc/pcie-rcar-gen4.c | |
| parent | a4179c60a993671b52b5ff32a783316c6a7a2f9a (diff) | |
| parent | 2fccd11518f19571f3802f22d2aad6e72b254c3e (diff) | |
| download | linux-stable-fb3d102fc20b2f150fa9a0ba576cd44af79e3518.tar.gz linux-stable-fb3d102fc20b2f150fa9a0ba576cd44af79e3518.tar.bz2 linux-stable-fb3d102fc20b2f150fa9a0ba576cd44af79e3518.zip | |
Merge branch 'pci/controller/xilinx-ecam'
- Drop xilinx-nwl updates of bridge bus number fields, since PCI core
already does that (Thippeswamy Havalige)
- Update xilinx-nwl driver and ECAM size in devicetree example to allow up
to 256 buses (Thippeswamy Havalige)
* pci/controller/xilinx-ecam:
PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-rcar-gen4.c')
0 files changed, 0 insertions, 0 deletions