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| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2023-10-16 10:41:02 +0530 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-10-26 11:57:03 +0000 |
| commit | 2fccd11518f19571f3802f22d2aad6e72b254c3e (patch) | |
| tree | 2c503884d94020486dae9143ebc998bfdaba730a /drivers/pci/controller | |
| parent | 177692115f6f7abac90d05dfa9054f40818718c2 (diff) | |
| download | linux-stable-2fccd11518f19571f3802f22d2aad6e72b254c3e.tar.gz linux-stable-2fccd11518f19571f3802f22d2aad6e72b254c3e.tar.bz2 linux-stable-2fccd11518f19571f3802f22d2aad6e72b254c3e.zip | |
PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
The PCIe Root Port controller expects ECAM size to be set through software.
As such, update the value of the NWL_ECAM_VALUE_DEFAULT macro to 16 to
allow the controller to address the 256 MB ECAM region and, as such,
enable support for detecting up to 256 buses.
[kwilczynski: commit log]
Link: https://patchwork.kernel.org/project/linux-pci/patch/20231016051102.1180432-5-thippeswamy.havalige@amd.com/
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'drivers/pci/controller')
| -rw-r--r-- | drivers/pci/controller/pcie-xilinx-nwl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) |