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| author | Sumit Saxena <sumit.saxena@broadcom.com> | 2019-07-26 00:55:52 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-10-11 18:21:00 +0200 |
| commit | e7cf8cc79f93c5b7b410026ce4e3624da8752170 (patch) | |
| tree | a40161de689d227880068d696f2948bfe1f2d322 /drivers/pci | |
| parent | 956ce989c41f70f945a36827cf5c74a1439ef5ae (diff) | |
| download | linux-stable-e7cf8cc79f93c5b7b410026ce4e3624da8752170.tar.gz linux-stable-e7cf8cc79f93c5b7b410026ce4e3624da8752170.tar.bz2 linux-stable-e7cf8cc79f93c5b7b410026ce4e3624da8752170.zip | |
PCI: Restore Resizable BAR size bits correctly for 1MB BARs
commit d2182b2d4b71ff0549a07f414d921525fade707b upstream.
In a Resizable BAR Control Register, bits 13:8 control the size of the BAR.
The encoded values of these bits are as follows (see PCIe r5.0, sec
7.8.6.3):
Value BAR size
0 1 MB (2^20 bytes)
1 2 MB (2^21 bytes)
2 4 MB (2^22 bytes)
...
43 8 EB (2^63 bytes)
Previously we incorrectly set the BAR size bits for a 1 MB BAR to 0x1f
instead of 0, so devices that support that size, e.g., new megaraid_sas and
mpt3sas adapters, fail to initialize during resume from S3 sleep.
Correctly calculate the BAR size bits for Resizable BAR control registers.
Link: https://lore.kernel.org/r/20190725192552.24295-1-sumit.saxena@broadcom.com
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203939
Fixes: d3252ace0bc6 ("PCI: Restore resized BAR state on resume")
Signed-off-by: Sumit Saxena <sumit.saxena@broadcom.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org # v4.19+
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c65465385d8c..6384930a6749 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1366,7 +1366,7 @@ static void pci_restore_rebar_state(struct pci_dev *pdev) pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; res = pdev->resource + bar_idx; - size = order_base_2((resource_size(res) >> 20) | 1) - 1; + size = ilog2(resource_size(res)) - 20; ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT; pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl); |