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| author | Robin Murphy <robin.murphy@arm.com> | 2021-03-26 16:02:40 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-03-30 11:41:50 +0100 |
| commit | 11fa1dc8020a2a9e0c59998920092d4df3fb7308 (patch) | |
| tree | 3c4aedb11288ab7437b54941fb75623a65a7b0bf /drivers/perf | |
| parent | b88f5e9792cc320a511697dcba8890d032ee3ed3 (diff) | |
| download | linux-stable-11fa1dc8020a2a9e0c59998920092d4df3fb7308.tar.gz linux-stable-11fa1dc8020a2a9e0c59998920092d4df3fb7308.tar.bz2 linux-stable-11fa1dc8020a2a9e0c59998920092d4df3fb7308.zip | |
perf/arm_pmu_platform: Use dev_err_probe() for IRQ errors
By virtue of using platform_irq_get_optional() under the covers,
platform_irq_count() needs the target interrupt controller to be
available and may return -EPROBE_DEFER if it isn't. Let's use
dev_err_probe() to avoid a spurious error log (and help debug any
deferral issues) in that case.
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/073d5e0d3ed1f040592cb47ca6fe3759f40cc7d1.1616774562.git.robin.murphy@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/arm_pmu_platform.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/perf/arm_pmu_platform.c b/drivers/perf/arm_pmu_platform.c index 933bd8410fc2..bb6ae955083a 100644 --- a/drivers/perf/arm_pmu_platform.c +++ b/drivers/perf/arm_pmu_platform.c @@ -6,6 +6,7 @@ * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> */ #define pr_fmt(fmt) "hw perfevents: " fmt +#define dev_fmt pr_fmt #include <linux/bug.h> #include <linux/cpumask.h> @@ -100,10 +101,8 @@ static int pmu_parse_irqs(struct arm_pmu *pmu) struct pmu_hw_events __percpu *hw_events = pmu->hw_events; num_irqs = platform_irq_count(pdev); - if (num_irqs < 0) { - pr_err("unable to count PMU IRQs\n"); - return num_irqs; - } + if (num_irqs < 0) + return dev_err_probe(&pdev->dev, num_irqs, "unable to count PMU IRQs\n"); /* * In this case we have no idea which CPUs are covered by the PMU. |