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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-11-10 22:22:43 +0300 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2023-01-12 22:48:42 +0530 |
| commit | 5db2264006dd43fb212ad542520389ce5cb465d1 (patch) | |
| tree | fec2bc7d056e88422c24c9eeecef6df4aff2825e /drivers/phy/qualcomm | |
| parent | 3b4bf465dd34d57cec2b1757d1e2b2395fe08f6a (diff) | |
| download | linux-stable-5db2264006dd43fb212ad542520389ce5cb465d1.tar.gz linux-stable-5db2264006dd43fb212ad542520389ce5cb465d1.tar.bz2 linux-stable-5db2264006dd43fb212ad542520389ce5cb465d1.zip | |
phy: qcom-qmp-ufs: rename regs layout arrays
Rename regs layouts to follow the QMP PHY version.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20221110192248.873973-9-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 4 | ||||
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 |
2 files changed, 21 insertions, 16 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..43255e8bf038 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -8,6 +8,9 @@ #define QCOM_PHY_QMP_PCS_UFS_V5_H_ /* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_PHY_START 0x000 +#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V5_PCS_UFS_SW_RESET 0x008 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c @@ -21,6 +24,7 @@ #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_READY_STATUS 0x180 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 7ccd7f0b7311..3cf8f6e66ca2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -69,31 +69,32 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, - [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, -}; - -static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), @@ -645,7 +646,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = msm8996_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .no_pcs_sw_reset = true, }; @@ -667,7 +668,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { @@ -685,7 +686,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_ufsphy_regs_layout, + .regs = ufsphy_v3_regs_layout, .no_pcs_sw_reset = true, }; @@ -705,7 +706,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm6115_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .no_pcs_sw_reset = true, }; @@ -725,7 +726,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v4_regs_layout, }; static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { @@ -743,7 +744,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { @@ -761,7 +762,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static void qmp_ufs_configure_lane(void __iomem *base, |