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author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-21 10:14:10 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-21 10:14:10 -0800 |
commit | a547df99aad777c1807e23991fa2471693c0e4cc (patch) | |
tree | 8e0a198648483580c9a7aa40efa4927c282fa4b1 /drivers/pinctrl/pinctrl-at91.c | |
parent | 8e5096607280d4e103389bfe8f8b7decbf538ff6 (diff) | |
parent | fa8cf57c923e86a693a85aff1df579245a27cbb3 (diff) | |
download | linux-stable-a547df99aad777c1807e23991fa2471693c0e4cc.tar.gz linux-stable-a547df99aad777c1807e23991fa2471693c0e4cc.tar.bz2 linux-stable-a547df99aad777c1807e23991fa2471693c0e4cc.zip |
Merge tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull bulk pin control changes from Linus Walleij:
"This has been queued and tested for a while. Lots of action here,
like in the GPIO tree, embedded stuff like this is really hot now it
seems. Details in the signed tag. I'm especially happy about the
Qualcomm driver as it is used in such a huge subset of mobile handsets
out there, and these platforms in general need better upstream support
- New driver for the Qualcomm TLMM pin controller and its msm8x74
subdriver.
- New driver for the Broadcom Capri BCM281xx SoC.
- New subdriver for the imx25 pin controller.
- New subdriver for the Tegra124 pin controller.
- Lock GPIO lines as IRQs for select combined pin control and GPIO
drivers for baytrail and sirf.
- Some semi-big refactorings and extenstions to the sirf driver.
- Lots of patching, cleanup and fixing in the Renesas "PFC" driver
and associated subdrivers as usual. It is settling down a little
bit now it seems.
- Minor fixes and incremental updates here and there as usual"
* tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
pinctrl: sunxi: Honor GPIO output initial vaules
pinctrl: capri: add dependency on OF
ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs
ARM: pinctrl: Add Broadcom Capri pinctrl driver
pinctrl: Add pinctrl binding for Broadcom Capri SoCs
pinctrl: Add void * to pinctrl_pin_desc
pinctrl: st: Fix a typo in probe
pinctrl: Fix some typos and grammar issues in the documentation
pinctrl: sirf: lock IRQs when starting them
pinctrl: sirf: put gpio interrupt pin into input status automatically
pinctrl: sirf: use only one irq_domain for the whole device node
pinctrl: single: fix infinite loop caused by bad mask
pinctrl: single: fix pcs_disable with bits_per_mux
pinctrl: single: fix DT bindings documentation
pinctrl: as3722: Set pin to output mode for some function
pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync
pinctrl: sirf: fix the pins of sdmmc5 connected with TriG
pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6
pinctrl: sunxi: Add Allwinner A20 clock output pin functions
pinctrl/lantiq: fix typo
...
Diffstat (limited to 'drivers/pinctrl/pinctrl-at91.c')
-rw-r--r-- | drivers/pinctrl/pinctrl-at91.c | 48 |
1 files changed, 35 insertions, 13 deletions
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 943805185f3f..38c6f8b9790e 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -118,7 +118,7 @@ struct at91_pin_group { }; /** - * struct at91_pinctrl_mux_ops - describes an At91 mux ops group + * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group * on new IP with support for periph C and D the way to mux in * periph A and B has changed * So provide the right call back @@ -722,7 +722,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin; int div; - dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); + *config = 0; + dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); pio = pin_to_controller(info, pin_to_bank(pin_id)); pin = pin_id % MAX_NB_GPIO_PER_BANK; @@ -783,10 +784,35 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev, return 0; } +#define DBG_SHOW_FLAG(flag) do { \ + if (config & flag) { \ + if (num_conf) \ + seq_puts(s, "|"); \ + seq_puts(s, #flag); \ + num_conf++; \ + } \ +} while (0) + static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { + unsigned long config; + int ret, val, num_conf = 0; + + ret = at91_pinconf_get(pctldev, pin_id, &config); + + DBG_SHOW_FLAG(MULTI_DRIVE); + DBG_SHOW_FLAG(PULL_UP); + DBG_SHOW_FLAG(PULL_DOWN); + DBG_SHOW_FLAG(DIS_SCHMIT); + DBG_SHOW_FLAG(DEGLITCH); + DBG_SHOW_FLAG(DEBOUNCE); + if (config & DEBOUNCE) { + val = config >> DEBOUNCE_VAL_SHIFT; + seq_printf(s, "(%d)", val); + } + return; } static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, @@ -1339,13 +1365,11 @@ void at91_pinctrl_gpio_suspend(void) __raw_writel(backups[i], pio + PIO_IDR); __raw_writel(wakeups[i], pio + PIO_IER); - if (!wakeups[i]) { - clk_unprepare(gpio_chips[i]->clock); - clk_disable(gpio_chips[i]->clock); - } else { + if (!wakeups[i]) + clk_disable_unprepare(gpio_chips[i]->clock); + else printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); - } } } @@ -1361,10 +1385,8 @@ void at91_pinctrl_gpio_resume(void) pio = gpio_chips[i]->regbase; - if (!wakeups[i]) { - if (clk_prepare(gpio_chips[i]->clock) == 0) - clk_enable(gpio_chips[i]->clock); - } + if (!wakeups[i]) + clk_prepare_enable(gpio_chips[i]->clock); __raw_writel(wakeups[i], pio + PIO_IDR); __raw_writel(backups[i], pio + PIO_IER); @@ -1396,7 +1418,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) chained_irq_enter(chip, desc); for (;;) { /* Reading ISR acks pending (edge triggered) GPIO interrupts. - * When there none are pending, we're finished unless we need + * When there are none pending, we're finished unless we need * to process multiple banks (like ID_PIOCDE on sam9263). */ isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); @@ -1505,7 +1527,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node, prev = gpio_chips[at91_gpio->pioc_idx - 1]; /* The top level handler handles one bank of GPIOs, except - * on some SoC it can handles up to three... + * on some SoC it can handle up to three... * We only set up the handler for the first of the list. */ if (prev && prev->next == at91_gpio) |