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authorAlexandre Belloni <alexandre.belloni@bootlin.com>2018-11-09 20:57:00 +0100
committerSebastian Reichel <sebastian.reichel@collabora.com>2018-12-05 22:40:25 +0100
commit9afe62509b329dbd973b8fdcdf168ddc5b5098cb (patch)
tree5f88667a6a74b54ad5b7162fc5fe9329b04208af /drivers/power
parent76ee875c2f48c57cbafa35d9c3b34e7202a45a83 (diff)
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power: reset: ocelot: switch the SI to boot mode
Switch the SI to boot mode so on a warm reboot, the SI is able to access the flash. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Diffstat (limited to 'drivers/power')
-rw-r--r--drivers/power/reset/ocelot-reset.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index 5a13a5cc8188..419952c61fd0 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -26,6 +26,13 @@ struct ocelot_reset_context {
#define SOFT_CHIP_RST BIT(0)
+#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
+#define IF_SI_OWNER_MASK GENMASK(1, 0)
+#define IF_SI_OWNER_SISL 0
+#define IF_SI_OWNER_SIBM 1
+#define IF_SI_OWNER_SIMC 2
+#define IF_SI_OWNER_OFFSET 4
+
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
{
@@ -37,6 +44,11 @@ static int ocelot_restart_handle(struct notifier_block *this,
regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
CORE_RST_PROTECT, 0);
+ /* Make the SI back to boot mode */
+ regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
+ IF_SI_OWNER_MASK << IF_SI_OWNER_OFFSET,
+ IF_SI_OWNER_SIBM << IF_SI_OWNER_OFFSET);
+
writel(SOFT_CHIP_RST, ctx->base);
pr_emerg("Unable to restart system\n");