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author | Jes Sorensen <Jes.Sorensen@redhat.com> | 2014-11-30 16:04:55 -0500 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-12-02 16:40:00 -0800 |
commit | d3220b71185e4792ac40086ed357d8cb3f6cc3e7 (patch) | |
tree | e401284ab86a65226a21806a536907a8048726a4 /drivers/staging/rtl8723au | |
parent | 7114ca14fcd97c04980811fa2aa40d5f7f061c40 (diff) | |
download | linux-stable-d3220b71185e4792ac40086ed357d8cb3f6cc3e7.tar.gz linux-stable-d3220b71185e4792ac40086ed357d8cb3f6cc3e7.tar.bz2 linux-stable-d3220b71185e4792ac40086ed357d8cb3f6cc3e7.zip |
staging: rtl8732au: Partial clean up of rtl8723a_rf6052.c
Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/rtl8723au')
-rw-r--r-- | drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c | 229 |
1 files changed, 123 insertions, 106 deletions
diff --git a/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c b/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c index 2dc0886e5f90..1aad4384471c 100644 --- a/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c +++ b/drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c @@ -42,21 +42,6 @@ #include <rtl8723a_hal.h> #include <usb_ops_linux.h> -/*---------------------------Define Local Constant---------------------------*/ -/* Define local structure for debug!!!!! */ -struct rf_shadow_compare_map { - /* Shadow register value */ - u32 Value; - /* Compare or not flag */ - u8 Compare; - /* Record If it had ever modified unpredicted */ - u8 ErrorOrNot; - /* Recorver Flag */ - u8 Recorver; - /* */ - u8 Driver_Write; -}; - /*----------------------------------------------------------------------------- * Function: PHY_RF6052SetBandwidth() * @@ -71,20 +56,23 @@ struct rf_shadow_compare_map { * * Note: For RF type 0222D *---------------------------------------------------------------------------*/ -void rtl8723a_phy_rf6052set_bw( - struct rtw_adapter *Adapter, - enum ht_channel_width Bandwidth) /* 20M or 40M */ +void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter, + enum ht_channel_width Bandwidth) /* 20M or 40M */ { - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); switch (Bandwidth) { case HT_CHANNEL_WIDTH_20: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); + pHalData->RfRegChnlVal[0] = + (pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400; + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, + pHalData->RfRegChnlVal[0]); break; case HT_CHANNEL_WIDTH_40: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); + pHalData->RfRegChnlVal[0] = + (pHalData->RfRegChnlVal[0] & 0xfffff3ff); + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, + pHalData->RfRegChnlVal[0]); break; default: break; @@ -108,7 +96,8 @@ void rtl8723a_phy_rf6052set_bw( * *---------------------------------------------------------------------------*/ -void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerlevel) +void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, + u8 *pPowerlevel) { struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); struct dm_priv *pdmpriv = &pHalData->dmpriv; @@ -118,7 +107,8 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve u8 idx1, idx2; u8 *ptr; - /* According to SD3 eechou's suggestion, we need to disable turbo scan for RU. */ + /* According to SD3 eechou's suggestion, we need to disable + turbo scan for RU. */ /* Otherwise, external PA will be broken if power index > 0x20. */ if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA) TurboScanOff = true; @@ -131,29 +121,37 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve if (TurboScanOff) { for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); - /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ + TxAGC[idx1] = pPowerlevel[idx1] | + (pPowerlevel[idx1] << 8) | + (pPowerlevel[idx1] << 16) | + (pPowerlevel[idx1] << 24); + /* 2010/10/18 MH For external PA module. + We need to limit power index to be less + than 0x20. */ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) TxAGC[idx1] = 0x20; } } } else { -/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ -/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ -/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ +/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx + * power. It shall be determined by power training mechanism. */ +/* Currently, we cannot fully disable driver dynamic tx power + * mechanism because it is referenced by BT coexist mechanism. */ +/* In the future, two mechanism shall be separated from each other + * and maintained independantly. Thanks for Lanhsin's reminder. */ if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { TxAGC[RF_PATH_A] = 0x10101010; TxAGC[RF_PATH_B] = 0x10101010; - } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { + } else if (pdmpriv->DynamicTxHighPowerLvl == + TxHighPwrLevel_Level2) { TxAGC[RF_PATH_A] = 0x00000000; TxAGC[RF_PATH_B] = 0x00000000; } else { for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); + TxAGC[idx1] = pPowerlevel[idx1] | + (pPowerlevel[idx1] << 8) | + (pPowerlevel[idx1] << 16) | + (pPowerlevel[idx1] << 24); } if (pHalData->EEPROMRegulatory == 0) { @@ -178,29 +176,24 @@ void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerleve } /* rf-A cck tx power */ - tmpval = TxAGC[RF_PATH_A]&0xff; + tmpval = TxAGC[RF_PATH_A] & 0xff; PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); - tmpval = TxAGC[RF_PATH_A]>>8; + tmpval = TxAGC[RF_PATH_A] >> 8; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); /* rf-B cck tx power */ - tmpval = TxAGC[RF_PATH_B]>>24; + tmpval = TxAGC[RF_PATH_B] >> 24; PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); - tmpval = TxAGC[RF_PATH_B]&0x00ffffff; + tmpval = TxAGC[RF_PATH_B] & 0x00ffffff; PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); } /* PHY_RF6052SetCckTxPower */ /* powerbase0 for OFDM rates */ /* powerbase1 for HT MCS rates */ -static void getPowerBase( - struct rtw_adapter *Adapter, - u8 *pPowerLevel, - u8 Channel, - u32 *OfdmBase, - u32 *MCSBase - ) +static void getPowerBase(struct rtw_adapter *Adapter, u8 *pPowerLevel, + u8 Channel, u32 *OfdmBase, u32 *MCSBase) { - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); u32 powerBase0, powerBase1; u8 Legacy_pwrdiff = 0; s8 HT20_pwrdiff = 0; @@ -211,8 +204,9 @@ static void getPowerBase( Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1]; powerBase0 = powerlevel[i] + Legacy_pwrdiff; - powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0; - *(OfdmBase+i) = powerBase0; + powerBase0 = powerBase0 << 24 | powerBase0 << 16 | + powerBase0 << 8 | powerBase0; + *(OfdmBase + i) = powerBase0; } for (i = 0; i < 2; i++) { @@ -222,36 +216,35 @@ static void getPowerBase( powerlevel[i] += HT20_pwrdiff; } powerBase1 = powerlevel[i]; - powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1; - *(MCSBase+i) = powerBase1; + powerBase1 = powerBase1 << 24 | powerBase1 << 16 | + powerBase1 << 8 | powerBase1; + *(MCSBase + i) = powerBase1; } } -static void getTxPowerWriteValByRegulatory( - struct rtw_adapter *Adapter, - u8 Channel, - u8 index, - u32 *powerBase0, - u32 *powerBase1, - u32 *pOutWriteVal - ) +static void +getTxPowerWriteValByRegulatory(struct rtw_adapter *Adapter, u8 Channel, + u8 index, u32 *powerBase0, u32 *powerBase1, + u32 *pOutWriteVal) { - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); struct dm_priv *pdmpriv = &pHalData->dmpriv; - u8 i, chnlGroup = 0, pwr_diff_limit[4]; - u32 writeVal, customer_limit, rf; + u8 i, chnlGroup = 0, pwr_diff_limit[4]; + u32 writeVal, customer_limit, rf; /* Index 0 & 1 = legacy OFDM, 2-5 = HT_MCS rate */ for (rf = 0; rf < 2; rf++) { switch (pHalData->EEPROMRegulatory) { case 0: /* Realtek better performance */ - /* increase power diff defined by Realtek for large power */ + /* increase power diff defined by Realtek for + * large power */ chnlGroup = 0; writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ((index < 2) ? powerBase0[rf] : powerBase1[rf]); break; case 1: /* Realtek regulatory */ - /* increase power diff defined by Realtek for regulatory */ + /* increase power diff defined by Realtek for + * regulatory */ if (pHalData->pwrGroupCnt == 1) chnlGroup = 0; if (pHalData->pwrGroupCnt >= 3) { @@ -262,17 +255,20 @@ static void getTxPowerWriteValByRegulatory( else if (Channel > 9) chnlGroup = 2; - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) + if (pHalData->CurrentChannelBW == + HT_CHANNEL_WIDTH_20) chnlGroup++; else chnlGroup += 4; } writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + - ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + ((index < 2) ? powerBase0[rf] : + powerBase1[rf]); break; case 2: /* Better regulatory */ - /* don't increase any power diff */ - writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]); + /* don't increase any power diff */ + writeVal = ((index < 2) ? powerBase0[rf] : + powerBase1[rf]); break; case 3: /* Customer defined power diff. */ chnlGroup = 0; @@ -299,28 +295,34 @@ static void getTxPowerWriteValByRegulatory( break; } -/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ -/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ -/* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ +/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. + It shall be determined by power training mechanism. */ +/* Currently, we cannot fully disable driver dynamic tx power mechanism + because it is referenced by BT coexist mechanism. */ +/* In the future, two mechanism shall be separated from each other and + maintained independantly. Thanks for Lanhsin's reminder. */ if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) writeVal = 0x14141414; - else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + else if (pdmpriv->DynamicTxHighPowerLvl == + TxHighPwrLevel_Level2) writeVal = 0x00000000; - /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ - /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ + /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ + /* This mechanism is only applied when + Driver-Highpower-Mechanism is OFF. */ if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) writeVal = writeVal - 0x06060606; else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) writeVal = writeVal; - *(pOutWriteVal+rf) = writeVal; + *(pOutWriteVal + rf) = writeVal; } } -static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue) +static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, + u32 *pValue) { - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, @@ -338,12 +340,13 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue for (rf = 0; rf < 2; rf++) { writeVal = pValue[rf]; for (i = 0; i < 4; i++) { - pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); - if (pwr_val[i] > RF6052_MAX_TX_PWR) + pwr_val[i] = (u8)((writeVal & + (0x7f << (i * 8))) >> (i * 8)); + if (pwr_val[i] > RF6052_MAX_TX_PWR) pwr_val[i] = RF6052_MAX_TX_PWR; } - writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | - (pwr_val[1]<<8) | pwr_val[0]; + writeVal = pwr_val[3] << 24 | pwr_val[2] << 16 | + pwr_val[1] << 8 | pwr_val[0]; if (rf == 0) RegOffset = RegOffset_A[index]; @@ -352,7 +355,8 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); - /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ + /* 201005115 Joseph: Set Tx Power diff for Tx power + training mechanism. */ if (((pHalData->rf_type == RF_2T2R) && (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12)) || @@ -360,15 +364,19 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04))) { writeVal = pwr_val[3]; - if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) + if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || + RegOffset == rTxAGC_A_Mcs07_Mcs04) RegOffset = 0xc90; - if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) + if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || + RegOffset == rTxAGC_B_Mcs07_Mcs04) RegOffset = 0xc98; for (i = 0; i < 3; i++) { if (i != 2) - writeVal = (writeVal > 8) ? (writeVal-8) : 0; + writeVal = (writeVal > 8) ? + (writeVal - 8) : 0; else - writeVal = (writeVal > 6) ? (writeVal-6) : 0; + writeVal = (writeVal > 6) ? + (writeVal - 6) : 0; rtl8723au_write8(Adapter, RegOffset + i, (u8)writeVal); } @@ -379,8 +387,9 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue * Function: PHY_RF6052SetOFDMTxPower * * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for - * different channel and read original value in TX power register area from - * 0xe00. We increase offset and original value to be correct tx pwr. + * different channel and read original value in TX power + * register area from 0xe00. We increase offset and + * original value to be correct tx pwr. * * Input: NONE * @@ -389,20 +398,23 @@ static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue * Return: NONE * * Revised History: - * When Who Remark - * 11/05/2008 MHC Simulate 8192 series method. - * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to - * A/B pwr difference or legacy/HT pwr diff. - * 2. We concern with path B legacy/HT OFDM difference. - * 01/22/2009 MHC Support new EPRO format from SD3. + * When Remark + * 11/05/2008 MHC Simulate 8192 series method. + * 01/06/2009 MHC 1. Prevent Path B tx power overflow or + * underflow dure to A/B pwr difference or + * legacy/HT pwr diff. + * 2. We concern with path B legacy/HT OFDM difference. + * 01/22/2009 MHC Support new EPRO format from SD3. * *---------------------------------------------------------------------------*/ -void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, u8 *pPowerLevel, u8 Channel) +void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, + u8 *pPowerLevel, u8 Channel) { u32 writeVal[2], powerBase0[2], powerBase1[2]; u8 index = 0; - getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]); + getPowerBase(Adapter, pPowerLevel, Channel, + &powerBase0[0], &powerBase1[0]); for (index = 0; index < 6; index++) { getTxPowerWriteValByRegulatory(Adapter, Channel, index, @@ -416,7 +428,7 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) { u32 u4RegValue = 0; u8 eRFPath; - struct bb_reg_define *pPhyReg; + struct bb_reg_define *pPhyReg; int rtStatus = _SUCCESS; struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); @@ -430,15 +442,17 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) /*----Store original RFENV control type----*/ switch (eRFPath) { case RF_PATH_A: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, + bRFSI_RFENV); break; case RF_PATH_B: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, + bRFSI_RFENV << 16); break; } /*----Set RF_ENV enable----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); + PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); udelay(1);/* PlatformStallExecution(1); */ /*----Set RF_ENV output high----*/ @@ -446,10 +460,12 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) udelay(1);/* PlatformStallExecution(1); */ /* Set bit number of Address and Data for RF register */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, + 0x0); /* Set 1 to 4 bits for 8255 */ udelay(1);/* PlatformStallExecution(1); */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, + 0x0); /* Set 0 to 12 bits for 8255 */ udelay(1);/* PlatformStallExecution(1); */ /*----Initialize RF fom connfiguration file----*/ @@ -464,15 +480,16 @@ static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter) /*----Restore RFENV control type----*/; switch (eRFPath) { case RF_PATH_A: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, + bRFSI_RFENV, u4RegValue); break; case RF_PATH_B: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, + bRFSI_RFENV << 16, u4RegValue); break; } if (rtStatus != _SUCCESS) { - /* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */ goto phy_RF6052_Config_ParaFile_Fail; } } |