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| author | Erwan Le Ray <erwan.leray@foss.st.com> | 2021-03-04 17:23:05 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-03-10 09:34:11 +0100 |
| commit | 315e2d8a125ad77a1bc28f621162713f3e7aef48 (patch) | |
| tree | cb6fb72e2bb84a282d29d0526c7ec726815c3664 /drivers/tty/serial/stm32-usart.c | |
| parent | f16b90c2d9db3e6ac719d1946b9d335ca4ab33f3 (diff) | |
| download | linux-stable-315e2d8a125ad77a1bc28f621162713f3e7aef48.tar.gz linux-stable-315e2d8a125ad77a1bc28f621162713f3e7aef48.tar.bz2 linux-stable-315e2d8a125ad77a1bc28f621162713f3e7aef48.zip | |
serial: stm32: fix FIFO flush in startup and set_termios
Fifo flush set USART_RQR register by calling stm32_usart_set_bits
routine (Read/Modify/Write). USART_RQR register is a write only
register. So, read before write isn't correct / relevant to flush
the FIFOs.
Replace stm32_usart_set_bits call by writel_relaxed.
Fixes: 84872dc448fe ("serial: stm32: add RX and TX FIFO flush")
Signed-off-by: Erwan Le Ray <erwan.leray@foss.st.com>
Link: https://lore.kernel.org/r/20210304162308.8984-11-erwan.leray@foss.st.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/stm32-usart.c')
| -rw-r--r-- | drivers/tty/serial/stm32-usart.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 2bdd04a47f91..183c76ddb165 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -657,7 +657,7 @@ static int stm32_usart_startup(struct uart_port *port) /* RX FIFO Flush */ if (ofs->rqr != UNDEF_REG) - stm32_usart_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); + writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); /* RX enabling */ val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); @@ -762,8 +762,8 @@ static void stm32_usart_set_termios(struct uart_port *port, /* flush RX & TX FIFO */ if (ofs->rqr != UNDEF_REG) - stm32_usart_set_bits(port, ofs->rqr, - USART_RQR_TXFRQ | USART_RQR_RXFRQ); + writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ, + port->membase + ofs->rqr); cr1 = USART_CR1_TE | USART_CR1_RE; if (stm32_port->fifoen) |