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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2018-09-13 10:21:25 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-09-18 16:07:24 +0200 |
| commit | 1ff3652bc7111df26b5807037f624be294cf69d5 (patch) | |
| tree | 344b23b8e50d8bf6c4e0efcc69809f31ea5c8a36 /drivers/tty | |
| parent | 3d8b43ad9c0cf023dd12458f23250c1b86b21e4e (diff) | |
| download | linux-stable-1ff3652bc7111df26b5807037f624be294cf69d5.tar.gz linux-stable-1ff3652bc7111df26b5807037f624be294cf69d5.tar.bz2 linux-stable-1ff3652bc7111df26b5807037f624be294cf69d5.zip | |
serial: samsung: Enable baud clock for UART reset procedure in resume
Ensure that the baud clock is also enabled for UART register writes in
driver resume. On Exynos5433 SoC this is needed to avoid external abort
issue.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/samsung.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 2f8fa184aafa..da1bd4bba8a9 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1941,7 +1941,11 @@ static int s3c24xx_serial_resume(struct device *dev) if (port) { clk_prepare_enable(ourport->clk); + if (!IS_ERR(ourport->baudclk)) + clk_prepare_enable(ourport->baudclk); s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); + if (!IS_ERR(ourport->baudclk)) + clk_disable_unprepare(ourport->baudclk); clk_disable_unprepare(ourport->clk); uart_resume_port(&s3c24xx_uart_drv, port); @@ -1964,7 +1968,11 @@ static int s3c24xx_serial_resume_noirq(struct device *dev) if (rx_enabled(port)) uintm &= ~S3C64XX_UINTM_RXD_MSK; clk_prepare_enable(ourport->clk); + if (!IS_ERR(ourport->baudclk)) + clk_prepare_enable(ourport->baudclk); wr_regl(port, S3C64XX_UINTM, uintm); + if (!IS_ERR(ourport->baudclk)) + clk_disable_unprepare(ourport->baudclk); clk_disable_unprepare(ourport->clk); } } |