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| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2021-07-16 07:01:27 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-07-21 09:50:27 +0200 |
| commit | c4a0f7a6ab5417eb6105b0e1d7e6e67f6ef7d4e5 (patch) | |
| tree | c76e19bf4a054c1bcb733d599a8f38c8b8a73b65 /drivers/usb/dwc2/params.c | |
| parent | 5719df243e118fb343725e8b2afb1637e1af1373 (diff) | |
| download | linux-stable-c4a0f7a6ab5417eb6105b0e1d7e6e67f6ef7d4e5.tar.gz linux-stable-c4a0f7a6ab5417eb6105b0e1d7e6e67f6ef7d4e5.tar.bz2 linux-stable-c4a0f7a6ab5417eb6105b0e1d7e6e67f6ef7d4e5.zip | |
usb: dwc2: Skip clock gating on Samsung SoCs
Commit 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr
function.") changed the way the driver handles power down modes in a such
way that it uses clock gating when no other power down mode is available.
This however doesn't work well on the DWC2 implementation used on the
Samsung SoCs. When a clock gating is enabled, system hangs. It looks that
the proper clock gating requires some additional glue code in the shared
USB2 PHY and/or Samsung glue code for the DWC2. To restore driver
operation on the Samsung SoCs simply skip enabling clock gating mode
until one finds what is really needed to make it working reliably.
Fixes: 0112b7ce68ea ("usb: dwc2: Update dwc2_handle_usb_suspend_intr function.")
Cc: stable <stable@vger.kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20210716050127.4406-1-m.szyprowski@samsung.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/dwc2/params.c')
| -rw-r--r-- | drivers/usb/dwc2/params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index 67c5eb140232..59e119345994 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) struct dwc2_core_params *p = &hsotg->params; p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + p->no_clock_gating = true; p->phy_utmi_width = 8; } |