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| author | Sebastian Reichel <sebastian.reichel@collabora.com> | 2023-10-20 16:11:41 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-10-21 12:49:35 +0200 |
| commit | 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee (patch) | |
| tree | 2527327be5e4a4bac0b0a243ebc9b89c11f35b5a /drivers/usb/dwc3/core.c | |
| parent | 98bad5bc447ec962988a48c92f7d0f8c4dc473d2 (diff) | |
| download | linux-stable-97789b93b792fc97ad4476b79e0f38ffa8e7e0ee.tar.gz linux-stable-97789b93b792fc97ad4476b79e0f38ffa8e7e0ee.tar.bz2 linux-stable-97789b93b792fc97ad4476b79e0f38ffa8e7e0ee.zip | |
usb: dwc3: add optional PHY interface clocks
On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
requires two extra clocks to be enabled. Without these extra clocks
hot-plugging USB devices is broken.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/dwc3/core.c')
| -rw-r--r-- | drivers/usb/dwc3/core.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d25490965b27..0328c86ef806 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -854,8 +854,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) if (ret) goto disable_ref_clk; + ret = clk_prepare_enable(dwc->utmi_clk); + if (ret) + goto disable_susp_clk; + + ret = clk_prepare_enable(dwc->pipe_clk); + if (ret) + goto disable_utmi_clk; + return 0; +disable_utmi_clk: + clk_disable_unprepare(dwc->utmi_clk); +disable_susp_clk: + clk_disable_unprepare(dwc->susp_clk); disable_ref_clk: clk_disable_unprepare(dwc->ref_clk); disable_bus_clk: @@ -865,6 +877,8 @@ disable_bus_clk: static void dwc3_clk_disable(struct dwc3 *dwc) { + clk_disable_unprepare(dwc->pipe_clk); + clk_disable_unprepare(dwc->utmi_clk); clk_disable_unprepare(dwc->susp_clk); clk_disable_unprepare(dwc->ref_clk); clk_disable_unprepare(dwc->bus_clk); @@ -1873,6 +1887,20 @@ static int dwc3_get_clocks(struct dwc3 *dwc) } } + /* specific to Rockchip RK3588 */ + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); + if (IS_ERR(dwc->utmi_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), + "could not get utmi clock\n"); + } + + /* specific to Rockchip RK3588 */ + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); + if (IS_ERR(dwc->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), + "could not get pipe clock\n"); + } + return 0; } |