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| author | Piyush Mehta <piyush.mehta@amd.com> | 2022-09-20 10:52:34 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-09-22 15:52:30 +0200 |
| commit | 031cba1695d4d3767ba47718077e83f2b5aac944 (patch) | |
| tree | 8eca505f0673a22fbf6e5f91df2868a07f41082a /drivers/usb | |
| parent | fc4ade55c617dc73c7e9756b57f3230b4ff24540 (diff) | |
| download | linux-stable-031cba1695d4d3767ba47718077e83f2b5aac944.tar.gz linux-stable-031cba1695d4d3767ba47718077e83f2b5aac944.tar.bz2 linux-stable-031cba1695d4d3767ba47718077e83f2b5aac944.zip | |
dt-bindings: usb: snps,dwc3: Add 'snps,resume-hs-terminations' quirk
Add a new 'snps,resume-hs-terminations' DT quirk to dwc3 core to resolved
issue of CRC failed error.
On the resume path, U3/U2 exit controller fails to send proper CRC checksum
in CRC5 field. As result Transaction Error is generated. Enabling bit 10 of
GUCTL1 will correct this problem.
When this bit is set to '1', the UTMI/ULPI opmode will be changed to
"normal" along with HS terminations and term/xcvr select signals after EOR.
This option is to support certain legacy UTMI/ULPI PHYs.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Link: https://lore.kernel.org/r/20220920052235.194272-2-piyush.mehta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb')
0 files changed, 0 insertions, 0 deletions