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| author | Evan Quan <evan.quan@amd.com> | 2019-01-21 17:57:29 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-01-25 16:15:35 -0500 |
| commit | 0bcaefa6bfc2e11b6d32675c872d765ba69cd9d0 (patch) | |
| tree | d20170c7d796f8bb418fd6610cc9bd22a6c1f6bb /drivers | |
| parent | 8ce84d4341e3abf8bc651c74f6312153c353bca8 (diff) | |
| download | linux-stable-0bcaefa6bfc2e11b6d32675c872d765ba69cd9d0.tar.gz linux-stable-0bcaefa6bfc2e11b6d32675c872d765ba69cd9d0.tar.bz2 linux-stable-0bcaefa6bfc2e11b6d32675c872d765ba69cd9d0.zip | |
drm/amd/display: change the max clock level to 16
As the gfxclk for SMU11 can have at most 16 discrete levels.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 9afd36a031a9..77200711abbe 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -92,7 +92,7 @@ enum dm_pp_clock_type { (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ "Invalid" -#define DM_PP_MAX_CLOCK_LEVELS 8 +#define DM_PP_MAX_CLOCK_LEVELS 16 struct dm_pp_clock_levels { uint32_t num_levels; |