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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-08-11 09:06:11 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:40:25 -0500 |
| commit | 2985bedc1c59441f4b0d4724a1c2211e0b6b4a19 (patch) | |
| tree | 17e19db1b20bb7a300561b9d32d194014788a0b3 /drivers | |
| parent | be6dd3c8e884f7b1a9f76c3ad1efd068b981f7d5 (diff) | |
| download | linux-stable-2985bedc1c59441f4b0d4724a1c2211e0b6b4a19.tar.gz linux-stable-2985bedc1c59441f4b0d4724a1c2211e0b6b4a19.tar.bz2 linux-stable-2985bedc1c59441f4b0d4724a1c2211e0b6b4a19.zip | |
drm/xe/xe2: Define Xe2_LPG IP features
Define a common set of Xe2 graphics feature flags and definitions that
will be used for all platforms in this family.
Several of the feature flags are inherited unchanged from Xe_HP and/or
Xe_HPC platforms:
- dma_mask_size remains 46 (Bspec 70817)
- supports_usm=1 (Bspec 59651)
- has_flatccs=1 (Bspec 58797)
- has_asid=1 (Bspec 59654, 59265, 60288)
- has_range_tlb_invalidate=1 (Bspec 71126)
However some of them still need proper implementation in the driver to
be used, so they are disabled.
Notable Xe2-specific changes:
- All Xe2 platforms use a five-level page table, regardless of the
virtual address space for the platform. (Bspec 59505)
The graphics engine mask represents the Xe2 architecture engines (Bspec
60149), but individual platforms may have a reduced set of usable
engines, as reflected by their fusing.
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pci.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index 32adeda3520c..46145340ae90 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -164,6 +164,24 @@ static const struct xe_graphics_desc graphics_xelpg = { .has_flat_ccs = 0, }; +#define XE2_GFX_FEATURES \ + .dma_mask_size = 46, \ + .has_asid = 1, \ + .has_flat_ccs = 0 /* FIXME: implementation missing */, \ + .has_range_tlb_invalidation = 1, \ + .supports_usm = 0 /* FIXME: implementation missing */, \ + .vm_max_level = 4, \ + .hw_engine_mask = \ + BIT(XE_HW_ENGINE_RCS0) | \ + BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ + GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) + +static const struct xe_graphics_desc graphics_xe2 = { + .name = "Xe2_LPG", + + XE2_GFX_FEATURES, +}; + static const struct xe_media_desc media_xem = { .name = "Xe_M", .ver = 12, @@ -296,6 +314,7 @@ static const struct xe_device_desc mtl_desc = { static struct gmdid_map graphics_ip_map[] = { { 1270, &graphics_xelpg }, { 1271, &graphics_xelpg }, + { 2004, &graphics_xe2 }, }; /* Map of GMD_ID values to media IP */ |