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| author | Huang Shijie <shijie8@gmail.com> | 2012-03-31 22:36:57 -0400 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2012-05-13 22:47:17 -0500 |
| commit | 4aa6ae3ecca04d7956817170418c74861ce071de (patch) | |
| tree | b5b21bafbb6088862e0a6bd9ef74fa0f30d99ac1 /drivers | |
| parent | 6d56b9d65813dd6a184efc5e7955d7e181a853c0 (diff) | |
| download | linux-stable-4aa6ae3ecca04d7956817170418c74861ce071de.tar.gz linux-stable-4aa6ae3ecca04d7956817170418c74861ce071de.tar.bz2 linux-stable-4aa6ae3ecca04d7956817170418c74861ce071de.zip | |
mtd: gpmi: do not include the mxs.h
The mxs.h does not exit in the mx6q.
So rewrite the __mxs_clrl()/__mxs_setl() and remove the mxs.h.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index e8ea7107932e..fa5200b8c895 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -21,7 +21,6 @@ #include <linux/mtd/gpmi-nand.h> #include <linux/delay.h> #include <linux/clk.h> -#include <mach/mxs.h> #include "gpmi-nand.h" #include "gpmi-regs.h" @@ -37,6 +36,8 @@ struct timing_threshod timing_default_threshold = { .max_dll_delay_in_ns = 16, }; +#define MXS_SET_ADDR 0x4 +#define MXS_CLR_ADDR 0x8 /* * Clear the bit and poll it cleared. This is usually called with * a reset address and mask being either SFTRST(bit 31) or CLKGATE @@ -47,7 +48,7 @@ static int clear_poll_bit(void __iomem *addr, u32 mask) int timeout = 0x400; /* clear the bit */ - __mxs_clrl(mask, addr); + writel(mask, addr + MXS_CLR_ADDR); /* * SFTRST needs 3 GPMI clocks to settle, the reference manual @@ -92,11 +93,11 @@ static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable) goto error; /* clear CLKGATE */ - __mxs_clrl(MODULE_CLKGATE, reset_addr); + writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR); if (!just_enable) { /* set SFTRST to reset the block */ - __mxs_setl(MODULE_SFTRST, reset_addr); + writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR); udelay(1); /* poll CLKGATE becoming set */ |