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authorYongqiang Sun <yongqiang.sun@amd.com>2017-11-10 15:40:52 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-12-06 12:48:09 -0500
commit675634c5aba341b2fee890fb93b3d3649ac5ce0b (patch)
treef0c755a3987dfb2fd05bd51fd843dc502ccee321 /drivers
parentdce46c53208f90cf5a401b62b17bbe2bc629c069 (diff)
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drm/amd/display: Only update output transfer function for full type.
dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be called within isr, check update flag before calling, only do it for full update. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c23
1 files changed, 16 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ad0e3b9be055..39869d379e3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1211,9 +1211,17 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
- else if (dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, &dpp->regamma_params))
- dpp->funcs->dpp_program_regamma_pwl(dpp, &dpp->regamma_params, OPP_REGAMMA_USER);
- else
+
+ /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
+ * update.
+ */
+ else if (dcn10_translate_regamma_to_hw_format(
+ stream->out_transfer_func,
+ &dpp->regamma_params)) {
+ dpp->funcs->dpp_program_regamma_pwl(
+ dpp,
+ &dpp->regamma_params, OPP_REGAMMA_USER);
+ } else
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
return true;
@@ -2076,16 +2084,17 @@ static void program_all_pipe_in_tree(
update_dchubp_dpp(dc, pipe_ctx, context);
- if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
+ if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
- }
- /*
+ /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+ * only do gamma programming for full update.
* TODO: This can be further optimized/cleaned up
* Always call this for now since it does memcmp inside before
* doing heavy calculation and programming
*/
- dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
+ if (pipe_ctx->plane_state->update_flags.bits.full_update)
+ dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
}
if (dc->debug.sanity_checks) {