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| author | Sridharan S N <quic_sridsn@quicinc.com> | 2023-06-23 10:27:55 +0530 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2023-07-12 13:34:27 +0200 |
| commit | 746b0f2675de6cc2197a9363873de7274c539d84 (patch) | |
| tree | f8d9f7349e923fe525028e62414567b053ceab52 /drivers | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
| download | linux-stable-746b0f2675de6cc2197a9363873de7274c539d84.tar.gz linux-stable-746b0f2675de6cc2197a9363873de7274c539d84.tar.bz2 linux-stable-746b0f2675de6cc2197a9363873de7274c539d84.zip | |
mtd: spinand: gigadevice: add support for GD5F1GQ{4,5}RExxH
Add support for:
GD5F1GQ5RExxH
GD5F1GQ4RExxH
Both are 1Gb SLC NAND flash with 4b/512b on-die ECC capability and has
2K + 64B PageSize.
Signed-off-by: Sridharan S N <quic_sridsn@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230623045757.30055-2-quic_sridsn@quicinc.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/spi/gigadevice.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index cfd7c3b26dc4..987710e09441 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -511,6 +511,26 @@ static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ5RExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4RExxH", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), + NAND_ECCREQ(4, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), }; static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { |