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| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-06-04 01:34:37 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-06-13 11:53:18 +0200 |
| commit | 75fe45a000a70ea35e2071eb7f8b873648590982 (patch) | |
| tree | 51cd50c41ab168aa00116aa566f772664889518c /drivers | |
| parent | 61a6737fcad8810258bdf1329f063b58ac27b230 (diff) | |
| download | linux-stable-75fe45a000a70ea35e2071eb7f8b873648590982.tar.gz linux-stable-75fe45a000a70ea35e2071eb7f8b873648590982.tar.bz2 linux-stable-75fe45a000a70ea35e2071eb7f8b873648590982.zip | |
clk: renesas: r8a779f0: Add SDHI0 clock
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 0aec5e8ffd96..e6f41b9f765a 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -128,6 +128,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER), DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), + DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), DEF_MOD("wdt", 907, R8A779F0_CLK_R), |