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authorMaxime Ripard <maxime@cerno.tech>2023-01-26 18:05:46 +0100
committerMaxime Ripard <maxime@cerno.tech>2023-02-16 10:24:10 +0100
commit89a173dec1b8951696b324880448d781d45f13ca (patch)
treedc688c57ba420ce7931921e32dfb7f3c07f22df1 /drivers
parentf56e0071a6fea6b416943d8736f3128c8b2abed2 (diff)
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drm/vc4: hdmi: Replace hardcoded value by define
The 120MHz value hardcoded in the call to max_t to compute the HSM rate is defined in the driver as HSM_MIN_CLOCK_FREQ, let's switch to it so that it's more readable. Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20230126-rpi-display-fw-clk-cleanup-v1-1-d646ff6fb842@cerno.tech Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/vc4/vc4_hdmi.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 14628864487a..98fa306dbd24 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -1482,7 +1482,9 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
* Additionally, the AXI clock needs to be at least 25% of
* pixel clock, but HSM ends up being the limiting factor.
*/
- hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
+ hsm_rate = max_t(unsigned long,
+ HSM_MIN_CLOCK_FREQ,
+ (tmds_char_rate / 100) * 101);
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
if (ret) {
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);