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author | Sumit Pundir <pundirsumit11@gmail.com> | 2018-01-06 20:35:24 +0530 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-01-08 16:03:43 +0100 |
commit | 96cf6b9c3c9db7ba63889f72bb8a8198731cc138 (patch) | |
tree | 7244fd93c37e1771e7bd4eeb8a43de7b81ec2b9e /drivers | |
parent | 04e491ca9df60ffe8637d00d68e5ab8bc73b30d5 (diff) | |
download | linux-stable-96cf6b9c3c9db7ba63889f72bb8a8198731cc138.tar.gz linux-stable-96cf6b9c3c9db7ba63889f72bb8a8198731cc138.tar.bz2 linux-stable-96cf6b9c3c9db7ba63889f72bb8a8198731cc138.zip |
Staging: iio: cdc: ad7152: Prefer using BIT macro
This patch fixes the following checkpatch.pl issue at multiple lines:
CHECK: Prefer using the BIT macro
Signed-off-by: Sumit Pundir <pundirsumit11@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/staging/iio/cdc/ad7152.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/staging/iio/cdc/ad7152.c b/drivers/staging/iio/cdc/ad7152.c index 59d1b35f6a4e..19dc896603a1 100644 --- a/drivers/staging/iio/cdc/ad7152.c +++ b/drivers/staging/iio/cdc/ad7152.c @@ -47,7 +47,7 @@ #define AD7152_STATUS_PWDN BIT(7) /* Setup Register Bit Designations (AD7152_REG_CHx_SETUP) */ -#define AD7152_SETUP_CAPDIFF (1 << 5) +#define AD7152_SETUP_CAPDIFF BIT(5) #define AD7152_SETUP_RANGE_2pF (0 << 6) #define AD7152_SETUP_RANGE_0_5pF (1 << 6) #define AD7152_SETUP_RANGE_1pF (2 << 6) @@ -55,8 +55,8 @@ #define AD7152_SETUP_RANGE(x) ((x) << 6) /* Config Register Bit Designations (AD7152_REG_CFG) */ -#define AD7152_CONF_CH2EN (1 << 3) -#define AD7152_CONF_CH1EN (1 << 4) +#define AD7152_CONF_CH2EN BIT(3) +#define AD7152_CONF_CH1EN BIT(4) #define AD7152_CONF_MODE_IDLE (0 << 0) #define AD7152_CONF_MODE_CONT_CONV (1 << 0) #define AD7152_CONF_MODE_SINGLE_CONV (2 << 0) @@ -64,7 +64,7 @@ #define AD7152_CONF_MODE_GAIN_CAL (6 << 0) /* Capdac Register Bit Designations (AD7152_REG_CAPDAC_XXX) */ -#define AD7152_CAPDAC_DACEN (1 << 7) +#define AD7152_CAPDAC_DACEN BIT(7) #define AD7152_CAPDAC_DACP(x) ((x) & 0x1F) /* CFG2 Register Bit Designations (AD7152_REG_CFG2) */ |