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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-01-20 10:20:52 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-01-30 16:46:00 -0800 |
| commit | a0c3ef2519b26368d6cdd178ad986a85d5c4bbf3 (patch) | |
| tree | 8742cec30d66c40723eebabb502622287562e04f /drivers | |
| parent | 72feb6f1eadee482c8ae96bbb2576fc9dd52de89 (diff) | |
| download | linux-stable-a0c3ef2519b26368d6cdd178ad986a85d5c4bbf3.tar.gz linux-stable-a0c3ef2519b26368d6cdd178ad986a85d5c4bbf3.tar.bz2 linux-stable-a0c3ef2519b26368d6cdd178ad986a85d5c4bbf3.zip | |
clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled
Instead of calling clk_prepare_enable() on a bunch of clocks at probe
time, set the CLK_IS_CRITICAL flag to the same as these are required
to be always on, and this is the right way of achieving that.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c index c9bf47e6098f..36553f0c13fe 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", + f_26m_adc_parents, 0x020, 0x024, 0x028, + 24, 1, 31, 0x1C0, 11, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, - 0x1C0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x030, 0x034, 0x038, + 0, 1, 7, 0x1C0, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", + sysaxi_parents, 0x030, 0x034, 0x038, + 8, 2, 15, 0x1C0, 13, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", + sysapb_parents, 0x030, 0x034, 0x038, + 16, 2, 23, 0x1C0, 14, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, 0x1C0, 15), @@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] = { MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, - 0x1C0, 22), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", + sgm_reg_parents, 0x050, 0x054, 0x058, + 16, 1, 23, 0x1C0, 22, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), /* CLK_CFG_6 */ @@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] = { f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, 0x1C0, 27), /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", + f_26m_adc_parents, 0x070, 0x074, 0x078, + 0, 1, 7, 0x1C0, 28, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", @@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(struct platform_device *pdev) ARRAY_SIZE(top_muxes), node, &mt7986_clk_lock, clk_data); - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { |