diff options
author | Robert Richter <rrichter@amd.com> | 2023-10-18 19:17:02 +0200 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2023-10-27 20:13:37 -0700 |
commit | a2fcb84a1978e4e855d632a07412030e99819cb8 (patch) | |
tree | 771b0c24703d625f7f5f9aaf98ae1742ab6d31fc /drivers | |
parent | f611d98a003644f76ad8fea7c3ca786a8ca69aff (diff) | |
download | linux-stable-a2fcb84a1978e4e855d632a07412030e99819cb8.tar.gz linux-stable-a2fcb84a1978e4e855d632a07412030e99819cb8.tar.bz2 linux-stable-a2fcb84a1978e4e855d632a07412030e99819cb8.zip |
cxl/port: Remove Component Register base address from struct cxl_port
The Component Register base address @component_reg_phys is no longer
used after the rework of the Component Register setup which now uses
struct member @reg_map instead. Remove the base address.
Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-10-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/cxl/core/port.c | 4 | ||||
-rw-r--r-- | drivers/cxl/cxl.h | 2 |
2 files changed, 1 insertions, 5 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 74e291ee3edd..8cb2ed0d6bbb 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -619,7 +619,6 @@ static int devm_cxl_link_parent_dport(struct device *host, static struct lock_class_key cxl_port_key; static struct cxl_port *cxl_port_alloc(struct device *uport_dev, - resource_size_t component_reg_phys, struct cxl_dport *parent_dport) { struct cxl_port *port; @@ -670,7 +669,6 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev, } else dev->parent = uport_dev; - port->component_reg_phys = component_reg_phys; ida_init(&port->decoder_ida); port->hdm_end = -1; port->commit_end = -1; @@ -746,7 +744,7 @@ static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *dev; int rc; - port = cxl_port_alloc(uport_dev, component_reg_phys, parent_dport); + port = cxl_port_alloc(uport_dev, parent_dport); if (IS_ERR(port)) return port; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 3a51b58a66d0..c07064e0c136 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -576,7 +576,6 @@ struct cxl_dax_region { * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation ordering * @commit_end: cursor to track highest committed decoder for commit ordering - * @component_reg_phys: component register capability base address (optional) * @dead: last ep has been removed, force port re-creation * @depth: How deep this port is relative to the root. depth 0 is the root. * @cdat: Cached CDAT data @@ -596,7 +595,6 @@ struct cxl_port { int nr_dports; int hdm_end; int commit_end; - resource_size_t component_reg_phys; bool dead; unsigned int depth; struct cxl_cdat { |