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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 19:23:43 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:02:26 +0200 |
| commit | cdc29f1088831fe87bf30f107214955f2b55dcbe (patch) | |
| tree | ad61861cf067be33ee3c12f7eb4c3e5dc474c8a2 /drivers | |
| parent | 599e16c1478dc6d08c0eef00e109e5b5c2315864 (diff) | |
| download | linux-stable-cdc29f1088831fe87bf30f107214955f2b55dcbe.tar.gz linux-stable-cdc29f1088831fe87bf30f107214955f2b55dcbe.tar.bz2 linux-stable-cdc29f1088831fe87bf30f107214955f2b55dcbe.zip | |
pinctrl: renesas: r8a779f0: Use shorthands for reserved fields
Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.
This reduces kernel size by 164 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c98e577996a71ae96145ee6da94aa18fd9ea85b9.1649865241.git.geert+renesas@glider.be
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a779f0.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c index 3b4ca9622bbe..55bdd38dfb25 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779f0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -1807,18 +1807,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32, - GROUP(4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2), + GROUP(-20, 2, 2, 2, 2, 2, 2), GROUP( - /* RESERVED 31, 30, 29, 28 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 27, 26, 25, 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 23, 22, 21, 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 19, 18, 17, 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 31-12 */ MOD_SEL1_11_10 MOD_SEL1_9_8 MOD_SEL1_7_6 |