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| author | Luo Jiaxing <luojiaxing@huawei.com> | 2020-01-20 20:22:33 +0800 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2020-01-20 19:31:14 -0500 |
| commit | d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee (patch) | |
| tree | 9d4aa548ee39b9e7a44a80b6532fd60b48a705dd /drivers | |
| parent | e9dc5e11c97ee981dac9ac5cd6f8f1c2384135ca (diff) | |
| download | linux-stable-d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee.tar.gz linux-stable-d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee.tar.bz2 linux-stable-d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee.zip | |
scsi: hisi_sas: Replace magic number when handle channel interrupt
We use magic number as offset and mask when handle channel interrupt, so
use macro to replace it.
Link: https://lore.kernel.org/r/1579522957-4393-4-git-send-email-john.garry@huawei.com
Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 34a3781a2a85..878530f6945f 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -495,6 +495,13 @@ struct hisi_sas_err_record_v3 { #define BASE_VECTORS_V3_HW 16 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) +#define CHNL_INT_STS_MSK 0xeeeeeeee +#define CHNL_INT_STS_PHY_MSK 0xe +#define CHNL_INT_STS_INT0_MSK BIT(1) +#define CHNL_INT_STS_INT1_MSK BIT(2) +#define CHNL_INT_STS_INT2_MSK BIT(3) +#define CHNL_WIDTH 4 + enum { DSM_FUNC_ERR_HANDLE_MSI = 0, }; @@ -1819,19 +1826,19 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) int phy_no = 0; irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) - & 0xeeeeeeee; + & CHNL_INT_STS_MSK; while (irq_msk) { - if (irq_msk & (2 << (phy_no * 4))) + if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH))) handle_chl_int0_v3_hw(hisi_hba, phy_no); - if (irq_msk & (4 << (phy_no * 4))) + if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH))) handle_chl_int1_v3_hw(hisi_hba, phy_no); - if (irq_msk & (8 << (phy_no * 4))) + if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH))) handle_chl_int2_v3_hw(hisi_hba, phy_no); - irq_msk &= ~(0xe << (phy_no * 4)); + irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH)); phy_no++; } |