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| author | Martin Leung <martin.leung@amd.com> | 2019-05-15 15:50:51 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:13 -0500 |
| commit | d8cd587d2bfd13dfc0dce6b74c1a78333415f413 (patch) | |
| tree | 0e169d0cb29d869701788c176051caa1861e6d97 /drivers | |
| parent | 03fd87db6d55b62a4771626a660a0df3d4a8546a (diff) | |
| download | linux-stable-d8cd587d2bfd13dfc0dce6b74c1a78333415f413.tar.gz linux-stable-d8cd587d2bfd13dfc0dce6b74c1a78333415f413.tar.bz2 linux-stable-d8cd587d2bfd13dfc0dce6b74c1a78333415f413.zip | |
drm/amd/display: removing MODULO change for dcn2
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error
[how]
removed code from dcn2
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index bf8cfd9b3e8f..c72aed35f4db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1046,41 +1046,13 @@ static const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = {108100, 108110, 108000, 1001, 1000},//108Mhz }; -static const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( - unsigned int pixel_rate_khz) -{ - int i; - - for (i = 0; i < NUM_ELEMENTS(video_optimized_pixel_rates); i++) { - const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; - - if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) { - return e; - } - } - - return NULL; -} - static bool dcn20_program_pix_clk( struct clock_source *clock_source, struct pixel_clk_params *pix_clk_params, struct pll_settings *pll_settings) { - struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); - unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; - unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; - const struct pixel_rate_range_table_entry *e = - look_up_in_video_optimized_rate_tlb(pll_settings->actual_pix_clk_100hz / 10); - dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings); - if (e) { - /* Set DTO values: phase = target clock, modulo = reference clock */ - REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); - REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); - } - return true; } |