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| author | Vandita Kulkarni <vandita.kulkarni@intel.com> | 2019-05-02 20:41:02 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2019-05-14 10:36:33 +0300 |
| commit | e3c54da0fe8654e7eb2ffd89d798288f83b46663 (patch) | |
| tree | bd1c73a0ac10b572eba191543eed8241b153c777 /drivers | |
| parent | 30bd7efdf678e92bee335d301d9d18e3f0209d3b (diff) | |
| download | linux-stable-e3c54da0fe8654e7eb2ffd89d798288f83b46663.tar.gz linux-stable-e3c54da0fe8654e7eb2ffd89d798288f83b46663.tar.bz2 linux-stable-e3c54da0fe8654e7eb2ffd89d798288f83b46663.zip | |
drm/i915: Fix pixel clock and crtc clock config mismatch
In case of dual link mode, the mode clock that we get
from the VBT is halved.
v2: Simplify the calculation (Jani).
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1556809862-31203-4-git-send-email-vandita.kulkarni@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/icl_dsi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index e94f951a8626..1e240ad665b5 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -1212,7 +1212,11 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder, /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ pipe_config->port_clock = cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); + pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; + if (intel_dsi->dual_link) + pipe_config->base.adjusted_mode.crtc_clock *= 2; + gen11_dsi_get_timings(encoder, pipe_config); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); |