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| author | Gustavo Sousa <gustavo.sousa@intel.com> | 2023-03-07 00:22:38 -0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2023-03-07 12:54:52 -0800 |
| commit | e67db9d2fd33e1118b518deab45dd6cdcf3c62a5 (patch) | |
| tree | 29e3bd48d1935099d884ef02fb99d29dea8201f2 /drivers | |
| parent | 6e9213287ce4d75765d2806986d4e3c7e4991b3b (diff) | |
| download | linux-stable-e67db9d2fd33e1118b518deab45dd6cdcf3c62a5.tar.gz linux-stable-e67db9d2fd33e1118b518deab45dd6cdcf3c62a5.tar.bz2 linux-stable-e67db9d2fd33e1118b518deab45dd6cdcf3c62a5.zip | |
drm/i915/xelp: Implement Wa_1606376872
Wa_1606376872 applies to all Xe_LP IPs except DG1.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230307032238.300674-1-gustavo.sousa@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 423e3e9c564b..97a60941eee5 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -480,6 +480,9 @@ #define HDC_FORCE_NON_COHERENT (1 << 4) #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) +#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) +#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) + #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 5a1c56c0901e..cf05eec1dc37 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_224, 0, false); - if (!IS_DG1(i915)) + if (!IS_DG1(i915)) { /* Wa_1806527549 */ wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); + + /* Wa_1606376872 */ + wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); + } } static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, |