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| author | Lijo Lazar <lijo.lazar@amd.com> | 2022-02-18 15:04:35 +0530 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 09:42:17 -0400 |
| commit | e6a02e2cc7fe3fec05eeaf08855e57d616a037e1 (patch) | |
| tree | 6e0c87f239d3bd56b93e4fc5810d12b0f955eb79 /drivers | |
| parent | 15091a6f4380a0c1a7202d52e82cdaaf80e2bb70 (diff) | |
| download | linux-stable-e6a02e2cc7fe3fec05eeaf08855e57d616a037e1.tar.gz linux-stable-e6a02e2cc7fe3fec05eeaf08855e57d616a037e1.tar.bz2 linux-stable-e6a02e2cc7fe3fec05eeaf08855e57d616a037e1.zip | |
drm/amdgpu: Add some XCC programming
Add additional XCC programming sequences.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index ce64c4fc5f1a..232feb387a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1150,6 +1150,29 @@ static void gfx_v9_4_3_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) WREG32_SOC15(GC, xcc_id, regCPC_PSP_DEBUG, data); } +static void gfx_v9_4_3_program_xcc_id(struct amdgpu_device *adev, int xcc_id) +{ + uint32_t tmp = 0; + + switch (adev->gfx.num_xcd) { + /* directly config VIRTUAL_XCC_ID to 0 for 1-XCC */ + case 1: + WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, 0x8); + break; + case 2: + tmp = (xcc_id % adev->gfx.num_xcc_per_xcp) << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, VIRTUAL_XCC_ID); + tmp = tmp | (adev->gfx.num_xcd << REG_FIELD_SHIFT(CP_HYP_XCP_CTL, NUM_XCC_IN_XCP)); + WREG32_SOC15(GC, xcc_id, regCP_HYP_XCP_CTL, tmp); + + tmp = xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, PHYSICAL_XCC_ID); + tmp = tmp | (xcc_id << REG_FIELD_SHIFT(CP_PSP_XCP_CTL, XCC_DIE_ID)); + WREG32_SOC15(GC, xcc_id, regCP_PSP_XCP_CTL, tmp); + break; + default: + break; + } +} + static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) { uint32_t rlc_setting; @@ -1948,6 +1971,9 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) return r; } + /* set the virtual and physical id based on partition_mode */ + gfx_v9_4_3_program_xcc_id(adev, i); + r = gfx_v9_4_3_kiq_resume(adev, i); if (r) return r; |