drm/amd/display: move dwb registers to header file

Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3 files changed, 289 insertions, 288 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
index 684241cb40d7..4ec5554f0f5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
@@ -29,32 +29,7 @@
 #include "resource.h"
 #include "dwb.h"
 #include "dcn10_dwb.h"
-#include "vega10/soc15ip.h"
-#include "raven1/DCN/dcn_1_0_offset.h"
-#include "raven1/DCN/dcn_1_0_sh_mask.h"
 
-/* DCN */
-#define BASE_INNER(seg) \
-	DCE_BASE__INST0_SEG ## seg
-
-#define BASE(seg) \
-	BASE_INNER(seg)
-
-#define SR(reg_name)\
-		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
-					mm ## reg_name
-
-#define SRI(reg_name, block, id)\
-	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-					mm ## block ## id ## _ ## reg_name
-
-
-#define SRII(reg_name, block, id)\
-	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
-					mm ## block ## id ## _ ## reg_name
-
-#define SF(reg_name, field_name, post_fix)\
-	.field_name = reg_name ## __ ## field_name ## post_fix
 
 #define REG(reg)\
 	dwbc10->dwbc_regs->reg
@@ -69,240 +44,6 @@
 #define TO_DCN10_DWBC(dwbc_base) \
 	container_of(dwbc_base, struct dcn10_dwbc, base)
 
-#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
-	SRI(WB_ENABLE, CNV, inst),\
-	SRI(WB_EC_CONFIG, CNV, inst),\
-	SRI(CNV_MODE, CNV, inst),\
-	SRI(WB_SOFT_RESET, CNV, inst),\
-	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
-	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
-	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
-	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
-	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
-	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
-	.DWB_SOURCE_SELECT = mmDWB_SOURCE_SELECT\
-
-#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
-	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
-	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
-	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
-	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
-	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
-	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
-	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
-
-#define DWBC_REG_FIELD_LIST(type) \
-	type WB_ENABLE;\
-	type DISPCLK_R_WB_GATE_DIS;\
-	type DISPCLK_G_WB_GATE_DIS;\
-	type DISPCLK_G_WBSCL_GATE_DIS;\
-	type WB_LB_LS_DIS;\
-	type WB_LB_SD_DIS;\
-	type WB_LUT_LS_DIS;\
-	type CNV_WINDOW_CROP_EN;\
-	type CNV_STEREO_TYPE;\
-	type CNV_INTERLACED_MODE;\
-	type CNV_EYE_SELECTION;\
-	type CNV_STEREO_POLARITY;\
-	type CNV_INTERLACED_FIELD_ORDER;\
-	type CNV_STEREO_SPLIT;\
-	type CNV_NEW_CONTENT;\
-	type CNV_FRAME_CAPTURE_EN;\
-	type WB_SOFT_RESET;\
-	type MCIF_WB_BUFMGR_ENABLE;\
-	type MCIF_WB_BUF_DUALSIZE_REQ;\
-	type MCIF_WB_BUFMGR_SW_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_INT_ACK;\
-	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
-	type MCIF_WB_BUFMGR_SW_LOCK;\
-	type MCIF_WB_P_VMID;\
-	type MCIF_WB_BUF_ADDR_FENCE_EN;\
-	type MCIF_WB_BUF_LUMA_PITCH;\
-	type MCIF_WB_BUF_CHROMA_PITCH;\
-	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
-	type MCIF_WB_TIME_PER_PIXEL;\
-	type WM_CHANGE_ACK_FORCE_ON;\
-	type MCIF_WB_CLI_WATERMARK_MASK;\
-	type MCIF_WB_BUF_1_ADDR_Y;\
-	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_1_ADDR_C;\
-	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_2_ADDR_Y;\
-	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_2_ADDR_C;\
-	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_3_ADDR_Y;\
-	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_3_ADDR_C;\
-	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
-	type MCIF_WB_BUF_4_ADDR_Y;\
-	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
-	type MCIF_WB_BUF_4_ADDR_C;\
-	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
-	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
-	type MCIF_WB_BUFMGR_VCE_INT_EN;\
-	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
-	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
-	type MCIF_WB_BUFMGR_VCE_LOCK;\
-	type MCIF_WB_BUFMGR_SLICE_SIZE;\
-	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
-	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
-	type NB_PSTATE_CHANGE_FORCE_ON;\
-	type NB_PSTATE_ALLOW_FOR_URGENT;\
-	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
-	type MCIF_WB_CLI_WATERMARK;\
-	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
-	type MCIF_WB_PITCH_SIZE_WARMUP;\
-	type MCIF_WB_BUF_LUMA_SIZE;\
-	type MCIF_WB_BUF_CHROMA_SIZE;\
-	type OPTC_DWB0_SOURCE_SELECT;\
-	type OPTC_DWB1_SOURCE_SELECT;\
-
-struct dcn10_dwbc_registers {
-	uint32_t WB_ENABLE;
-	uint32_t WB_EC_CONFIG;
-	uint32_t CNV_MODE;
-	uint32_t WB_SOFT_RESET;
-	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
-	uint32_t MCIF_WB_BUF_PITCH;
-	uint32_t MCIF_WB_ARBITRATION_CONTROL;
-	uint32_t MCIF_WB_SCLK_CHANGE;
-	uint32_t MCIF_WB_BUF_1_ADDR_Y;
-	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_1_ADDR_C;
-	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_2_ADDR_Y;
-	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_2_ADDR_C;
-	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_3_ADDR_Y;
-	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_3_ADDR_C;
-	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUF_4_ADDR_Y;
-	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
-	uint32_t MCIF_WB_BUF_4_ADDR_C;
-	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
-	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
-	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
-	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
-	uint32_t MCIF_WB_WATERMARK;
-	uint32_t MCIF_WB_WARM_UP_CNTL;
-	uint32_t MCIF_WB_BUF_LUMA_SIZE;
-	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
-	uint32_t DWB_SOURCE_SELECT;
-};
-struct dcn10_dwbc_mask {
-	DWBC_REG_FIELD_LIST(uint32_t)
-};
-struct dcn10_dwbc_shift {
-	DWBC_REG_FIELD_LIST(uint8_t)
-};
-struct dcn10_dwbc {
-	struct dwbc base;
-	const struct dcn10_dwbc_registers *dwbc_regs;
-	const struct dcn10_dwbc_shift *dwbc_shift;
-	const struct dcn10_dwbc_mask *dwbc_mask;
-};
-
-#define dwbc_regs(id)\
-[id] = {\
-	DWBC_COMMON_REG_LIST_DCN1_0(id),\
-}
-
-static const struct dcn10_dwbc_registers dwbc10_regs[] = {
-	dwbc_regs(0),
-	dwbc_regs(1),
-};
-
-static const struct dcn10_dwbc_shift dwbc10_shift = {
-	DWBC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
-};
-
-static const struct dcn10_dwbc_mask dwbc10_mask = {
-	DWBC_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
-};
-
-
 static bool get_caps(struct dwbc *dwbc, struct dwb_caps *caps)
 {
 	if (caps) {
@@ -603,7 +344,7 @@ const struct dwbc_funcs dcn10_dwbc_funcs = {
 	.reset_advanced_settings = reset_advanced_settings,
 };
 
-static void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
 						  struct dc_context *ctx,
 						  const struct dcn10_dwbc_registers *dwbc_regs,
 						  const struct dcn10_dwbc_shift *dwbc_shift,
@@ -620,32 +361,5 @@ static void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
 	dwbc10->dwbc_mask = dwbc_mask;
 }
 
-bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
-{
-	int i;
-	uint32_t pipe_count = pool->res_cap->num_dwb;
-
-	ASSERT(pipe_count > 0);
 
-	for (i = 0; i < pipe_count; i++) {
-		struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc));
-
-		if (!dwbc10)
-			return false;
-
-		dcn10_dwbc_construct(dwbc10, ctx,
-				&dwbc10_regs[i],
-				&dwbc10_shift,
-				&dwbc10_mask,
-				i);
-
-		pool->dwbc[i] = &dwbc10->base;
-		if (pool->dwbc[i] == NULL) {
-			BREAK_TO_DEBUGGER();
-			dm_error("DC: failed to create dwbc10!\n");
-			return false;
-		}
-	}
-	return true;
-}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
index cf530aed4e1c..1fdc2be42fa9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
@@ -26,7 +26,252 @@
 
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
 
-bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool);
+/* DCN */
+#define BASE_INNER(seg) \
+	DCE_BASE__INST0_SEG ## seg
+
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
+					mm ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+	.field_name = reg_name ## __ ## field_name ## post_fix
+
+
+#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \
+	SRI(WB_ENABLE, CNV, inst),\
+	SRI(WB_EC_CONFIG, CNV, inst),\
+	SRI(CNV_MODE, CNV, inst),\
+	SRI(WB_SOFT_RESET, CNV, inst),\
+	SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
+	SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\
+	SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\
+	SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\
+	SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\
+	.DWB_SOURCE_SELECT = mmDWB_SOURCE_SELECT\
+
+#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \
+	SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
+	SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\
+	SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\
+	SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\
+	SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
+
+#define DWBC_REG_FIELD_LIST(type) \
+	type WB_ENABLE;\
+	type DISPCLK_R_WB_GATE_DIS;\
+	type DISPCLK_G_WB_GATE_DIS;\
+	type DISPCLK_G_WBSCL_GATE_DIS;\
+	type WB_LB_LS_DIS;\
+	type WB_LB_SD_DIS;\
+	type WB_LUT_LS_DIS;\
+	type CNV_WINDOW_CROP_EN;\
+	type CNV_STEREO_TYPE;\
+	type CNV_INTERLACED_MODE;\
+	type CNV_EYE_SELECTION;\
+	type CNV_STEREO_POLARITY;\
+	type CNV_INTERLACED_FIELD_ORDER;\
+	type CNV_STEREO_SPLIT;\
+	type CNV_NEW_CONTENT;\
+	type CNV_FRAME_CAPTURE_EN;\
+	type WB_SOFT_RESET;\
+	type MCIF_WB_BUFMGR_ENABLE;\
+	type MCIF_WB_BUF_DUALSIZE_REQ;\
+	type MCIF_WB_BUFMGR_SW_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_INT_ACK;\
+	type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\
+	type MCIF_WB_BUFMGR_SW_LOCK;\
+	type MCIF_WB_P_VMID;\
+	type MCIF_WB_BUF_ADDR_FENCE_EN;\
+	type MCIF_WB_BUF_LUMA_PITCH;\
+	type MCIF_WB_BUF_CHROMA_PITCH;\
+	type MCIF_WB_CLIENT_ARBITRATION_SLICE;\
+	type MCIF_WB_TIME_PER_PIXEL;\
+	type WM_CHANGE_ACK_FORCE_ON;\
+	type MCIF_WB_CLI_WATERMARK_MASK;\
+	type MCIF_WB_BUF_1_ADDR_Y;\
+	type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_1_ADDR_C;\
+	type MCIF_WB_BUF_1_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_Y;\
+	type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_2_ADDR_C;\
+	type MCIF_WB_BUF_2_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_Y;\
+	type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_3_ADDR_C;\
+	type MCIF_WB_BUF_3_ADDR_C_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_Y;\
+	type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\
+	type MCIF_WB_BUF_4_ADDR_C;\
+	type MCIF_WB_BUF_4_ADDR_C_OFFSET;\
+	type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\
+	type MCIF_WB_BUFMGR_VCE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_INT_ACK;\
+	type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\
+	type MCIF_WB_BUFMGR_VCE_LOCK;\
+	type MCIF_WB_BUFMGR_SLICE_SIZE;\
+	type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\
+	type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\
+	type NB_PSTATE_CHANGE_FORCE_ON;\
+	type NB_PSTATE_ALLOW_FOR_URGENT;\
+	type NB_PSTATE_CHANGE_WATERMARK_MASK;\
+	type MCIF_WB_CLI_WATERMARK;\
+	type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\
+	type MCIF_WB_PITCH_SIZE_WARMUP;\
+	type MCIF_WB_BUF_LUMA_SIZE;\
+	type MCIF_WB_BUF_CHROMA_SIZE;\
+	type OPTC_DWB0_SOURCE_SELECT;\
+	type OPTC_DWB1_SOURCE_SELECT;\
+
+struct dcn10_dwbc_registers {
+	uint32_t WB_ENABLE;
+	uint32_t WB_EC_CONFIG;
+	uint32_t CNV_MODE;
+	uint32_t WB_SOFT_RESET;
+	uint32_t MCIF_WB_BUFMGR_SW_CONTROL;
+	uint32_t MCIF_WB_BUF_PITCH;
+	uint32_t MCIF_WB_ARBITRATION_CONTROL;
+	uint32_t MCIF_WB_SCLK_CHANGE;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y;
+	uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_1_ADDR_C;
+	uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y;
+	uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_2_ADDR_C;
+	uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y;
+	uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_3_ADDR_C;
+	uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y;
+	uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;
+	uint32_t MCIF_WB_BUF_4_ADDR_C;
+	uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;
+	uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;
+	uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;
+	uint32_t MCIF_WB_NB_PSTATE_CONTROL;
+	uint32_t MCIF_WB_WATERMARK;
+	uint32_t MCIF_WB_WARM_UP_CNTL;
+	uint32_t MCIF_WB_BUF_LUMA_SIZE;
+	uint32_t MCIF_WB_BUF_CHROMA_SIZE;
+	uint32_t DWB_SOURCE_SELECT;
+};
+struct dcn10_dwbc_mask {
+	DWBC_REG_FIELD_LIST(uint32_t)
+};
+struct dcn10_dwbc_shift {
+	DWBC_REG_FIELD_LIST(uint8_t)
+};
+struct dcn10_dwbc {
+	struct dwbc base;
+	const struct dcn10_dwbc_registers *dwbc_regs;
+	const struct dcn10_dwbc_shift *dwbc_shift;
+	const struct dcn10_dwbc_mask *dwbc_mask;
+};
+
+void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10,
+		struct dc_context *ctx,
+		const struct dcn10_dwbc_registers *dwbc_regs,
+		const struct dcn10_dwbc_shift *dwbc_shift,
+		const struct dcn10_dwbc_mask *dwbc_mask,
+		int inst);
+
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index ac6d01ec0505..298eb44ad9bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -326,6 +326,24 @@ static const struct dcn_dpp_mask tf_mask = {
 	TF_REG_LIST_SH_MASK_DCN10(_MASK),
 };
 
+#define dwbc_regs(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN1_0(id),\
+}
+
+static const struct dcn10_dwbc_registers dwbc10_regs[] = {
+	dwbc_regs(0),
+	dwbc_regs(1),
+};
+
+static const struct dcn10_dwbc_shift dwbc10_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
+};
+
+static const struct dcn10_dwbc_mask dwbc10_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
+};
+
 static const struct dcn_mpc_registers mpc_regs = {
 		MPC_COMMON_REG_LIST_DCN1_0(0),
 		MPC_COMMON_REG_LIST_DCN1_0(1),
@@ -1215,6 +1233,30 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx)
 	return value;
 }
 
+static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t dwb_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < dwb_count; i++) {
+		struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc));
+
+		if (!dwbc10) {
+			dm_error("DC: failed to create dwbc10!\n");
+			return false;
+		}
+
+		dcn10_dwbc_construct(dwbc10, ctx,
+				&dwbc10_regs[i],
+				&dwbc10_shift,
+				&dwbc10_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc10->base;
+	}
+	return true;
+}
+
 static bool construct(
 	uint8_t num_virtual_links,
 	struct dc *dc,