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| author | Aric Cyr <aric.cyr@amd.com> | 2020-07-27 21:21:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-10 18:08:36 -0400 |
| commit | a49f6727e14caff32419cc3002b9ae9cafb750d7 (patch) | |
| tree | d82b0b453629ccfe7b9c03cef2597cf7fedbe086 /fs/cachefiles | |
| parent | 97a9b60fa3bf29d29d0fc253a98096c02fb8106e (diff) | |
| download | linux-stable-a49f6727e14caff32419cc3002b9ae9cafb750d7.tar.gz linux-stable-a49f6727e14caff32419cc3002b9ae9cafb750d7.tar.bz2 linux-stable-a49f6727e14caff32419cc3002b9ae9cafb750d7.zip | |
drm/amd/display: Fix incorrect backlight register offset for DCN
[Why]
Typo in backlight refactor inctroduced wrong register offset.
[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV
Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'fs/cachefiles')
0 files changed, 0 insertions, 0 deletions