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| author | Ravi Bangoria <ravi.bangoria@amd.com> | 2022-05-09 10:19:09 +0530 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-05-11 16:27:10 +0200 |
| commit | ba5d35b442c65f32d38ef61f732218274c6dcf4c (patch) | |
| tree | 70a044c54e84ef07c4283f872e5e0e35934311e4 /fs/ext4/fast_commit.h | |
| parent | 2a7a7e658682bfd7501dc6b4c9d365aa6c79788a (diff) | |
| download | linux-stable-ba5d35b442c65f32d38ef61f732218274c6dcf4c.tar.gz linux-stable-ba5d35b442c65f32d38ef61f732218274c6dcf4c.tar.bz2 linux-stable-ba5d35b442c65f32d38ef61f732218274c6dcf4c.zip | |
perf/amd/ibs: Add support for L3 miss filtering
IBS L3 miss filtering works by tagging an instruction on IBS counter
overflow and generating an NMI if the tagged instruction causes an L3
miss. Samples without an L3 miss are discarded and counter is reset
with random value (between 1-15 for fetch pmu and 1-127 for op pmu).
This helps in reducing sampling overhead when user is interested only
in such samples. One of the use case of such filtered samples is to
feed data to page-migration daemon in tiered memory systems.
Add support for L3 miss filtering in IBS driver via new pmu attribute
"l3missonly". Example usage:
# perf record -a -e ibs_op/l3missonly=1/ --raw-samples sleep 5
Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220509044914.1473-4-ravi.bangoria@amd.com
Diffstat (limited to 'fs/ext4/fast_commit.h')
0 files changed, 0 insertions, 0 deletions