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authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>2022-04-08 10:10:04 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-04-25 17:06:16 -0400
commit89c342a9661838b9afe3988418705f877f496928 (patch)
tree93801b1b0839ef5e50f821d39a6fd466e365bfb6 /fs/ufs
parent259f249c4b9b2a9dc15095afd071bcc5b8d6f30e (diff)
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drm/amd/display: update dcn315 clk table read
Clean up the sequence by making sure clk_mgr always builds a reasonable clock table regardless of what we read from smu by moving all defaults from resource soc struct to clk_mgr. Now the only thing resource soc update does is read the clock table and apply any DC specific policy decisions to how clocks are populated in dml soc. Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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