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authorXu Yang <xu.yang_2@nxp.com>2023-04-18 18:29:08 +0800
committerWill Deacon <will@kernel.org>2023-06-09 12:01:10 +0100
commit55691f99d417084305e575c477f06556f93dfb0b (patch)
tree43f2fdd9fee64654d35f96f9c9842f10ba29db67 /fs/verity/init.c
parentd2e3bb51281875be23cb4726a59b03d0a53eb0d3 (diff)
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drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver
Add ddr performance monitor support for i.MX93. There are 11 counters for ddr performance events. - Counter 0 is a 64-bit counter that counts only clock cycles. - Counter 1-10 are 32-bit counters that can monitor counter-specific events in addition to counting reference events. For example: perf stat -a -e imx9_ddr0/ddrc_pm_1,counter=1/,imx9_ddr0/ddrc_pm_2,counter=2/ ls Besides, this ddr pmu support AXI filter capability. It's implemented as counter-specific events. It now supports read transaction, write transaction and read beat events which corresponding respecitively to counter 2, 3 and 4. axi_mask and axi_id need to be as event parameters. For example: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_trans_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/ perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_trans_filt,counter=3,axi_mask=ID_MASK,axi_id=ID/ perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt,counter=4,axi_mask=ID_MASK,axi_id=ID/ Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20230418102910.2065651-1-xu.yang_2@nxp.com [will: Remove redundant error message on platform_get_irq() failure] Signed-off-by: Will Deacon <will@kernel.org>
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