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author | eric miao <eric.miao@marvell.com> | 2008-02-14 15:48:23 +0800 |
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committer | David Woodhouse <dwmw2@infradead.org> | 2008-04-22 19:27:27 +0100 |
commit | fe69af002e26ca39824f626459c16d642607b573 (patch) | |
tree | 761c1bc2325eaed041a9fbe3a1fe18d9f6c9b988 /include/asm-arm/arch-pxa | |
parent | b73d7e4381311bea024bf7cedcba3dcf20f63aab (diff) | |
download | linux-stable-fe69af002e26ca39824f626459c16d642607b573.tar.gz linux-stable-fe69af002e26ca39824f626459c16d642607b573.tar.bz2 linux-stable-fe69af002e26ca39824f626459c16d642607b573.zip |
[MTD] [NAND] support for pxa3xx
This is preliminary since:
1. It supports only _one_ chip select at the moment. As there is no
existing platforms available using two chip selects of the NAND
controller, it shall really not include code for supporting the
2nd chip select for now, as such code cannot be verified.
2. It resorts to the default and simpliest memory based badblock
table
3. Only limited types of nand flash are currently supported. Most
PXA3xx processors come with on-chip NAND flash dies, so there
isn't much flexibility for other types of NAND.
4. The NAND controller should be configured to detect the device's
ID, thus making it difficult to use nand_scan_ident() to assist
the detection process (though it's not impossible)
TODO: fix all the above limitations of cuz :-)
Signed-off-by: eric miao <eric.miao@marvell.com>
Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r-- | include/asm-arm/arch-pxa/pxa3xx_nand.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa3xx_nand.h b/include/asm-arm/arch-pxa/pxa3xx_nand.h new file mode 100644 index 000000000000..81a8937486cb --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa3xx_nand.h @@ -0,0 +1,18 @@ +#ifndef __ASM_ARCH_PXA3XX_NAND_H +#define __ASM_ARCH_PXA3XX_NAND_H + +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> + +struct pxa3xx_nand_platform_data { + + /* the data flash bus is shared between the Static Memory + * Controller and the Data Flash Controller, the arbiter + * controls the ownership of the bus + */ + int enable_arbiter; + + struct mtd_partition *parts; + unsigned int nr_parts; +}; +#endif /* __ASM_ARCH_PXA3XX_NAND_H */ |