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authorThomas Abraham <thomas.ab@samsung.com>2014-07-14 19:08:34 +0530
committerTomasz Figa <t.figa@samsung.com>2014-07-26 02:50:15 +0200
commitca5b4029382245397dd6829c6321121cab1a1471 (patch)
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clk: samsung: register exynos5420 apll/kpll configuration data
Register the PLL configuration data for APLL and KPLL on Exynos5420. This configuration data table specifies PLL coefficients for supported PLL clock speeds when a 24MHz clock is supplied as the input clock source for these PLLs. Cc: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Tested-by: Arjun K.V <arjun.kv@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
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