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| author | Wadim Egorov <w.egorov@phytec.de> | 2018-02-14 17:07:11 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2018-02-14 15:33:43 -0500 |
| commit | 9708fb630d19ee51ae3aeb3a533e3010da0e8570 (patch) | |
| tree | 9880a5ca8dd4be46a8aeed9af6378d381bf8933b /include/dt-bindings/net | |
| parent | 37c64cf63ba1f9c071b37a2129ae9860fd423d6c (diff) | |
| download | linux-stable-9708fb630d19ee51ae3aeb3a533e3010da0e8570.tar.gz linux-stable-9708fb630d19ee51ae3aeb3a533e3010da0e8570.tar.bz2 linux-stable-9708fb630d19ee51ae3aeb3a533e3010da0e8570.zip | |
net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/dt-bindings/net')
| -rw-r--r-- | include/dt-bindings/net/ti-dp83867.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h index 172744a72eb7..7b1656427cbe 100644 --- a/include/dt-bindings/net/ti-dp83867.h +++ b/include/dt-bindings/net/ti-dp83867.h @@ -42,4 +42,18 @@ #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf +/* IO_MUX_CFG - Clock output selection */ +#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA +#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB +#define DP83867_CLK_O_SEL_REF_CLK 0xC #endif |