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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-17 11:29:18 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-17 11:29:18 -0700 |
| commit | e609f9f23e57f6af1c8f0b5759a87f9db3521eb1 (patch) | |
| tree | fb270968e6d49b2cf7fb70929d8cf7fd598a56c0 /include/dt-bindings/reset | |
| parent | 83dd720da666a2af6debbb2d8aab289e3b6cb8f5 (diff) | |
| parent | e7590308d17e578e47f298cc3fec359108341cb6 (diff) | |
| download | linux-stable-e609f9f23e57f6af1c8f0b5759a87f9db3521eb1.tar.gz linux-stable-e609f9f23e57f6af1c8f0b5759a87f9db3521eb1.tar.bz2 linux-stable-e609f9f23e57f6af1c8f0b5759a87f9db3521eb1.zip | |
Merge branch 'clk-fixes' into clk-next
* clk-fixes:
clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change
clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks
clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver
clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
clk: stm32f4: fix: exclude values 0 and 1 for PLLQ
Diffstat (limited to 'include/dt-bindings/reset')
0 files changed, 0 insertions, 0 deletions