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| author | Stephen Boyd <sboyd@kernel.org> | 2023-08-22 10:51:09 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-08-22 10:51:09 -0700 |
| commit | 438c61a7905abe9053e7f6411cd62b754b5ca4e1 (patch) | |
| tree | 9c2c30d878163740e9bbe2ee55a454bb16ba2920 /include/dt-bindings | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
| parent | 5c7a71fd82350c2f5828a66a1f2f38306d61cbc7 (diff) | |
| download | linux-stable-438c61a7905abe9053e7f6411cd62b754b5ca4e1.tar.gz linux-stable-438c61a7905abe9053e7f6411cd62b754b5ca4e1.tar.bz2 linux-stable-438c61a7905abe9053e7f6411cd62b754b5ca4e1.zip | |
Merge tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- PLL rates for rk3568 and the display clock tree for rv1126 which wasn't present before
* tag 'v6.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rv1126: Add PD_VO clock tree
clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz
clk: rockchip: rk3568: Add PLL rate for 101MHz
Diffstat (limited to 'include/dt-bindings')
0 files changed, 0 insertions, 0 deletions