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authorJernej Skrabec <jernej.skrabec@siol.net>2018-03-01 22:34:30 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-03-02 08:42:30 +0100
commit55de0f31df1a31b346edfe98d061f11162ff1ad4 (patch)
tree89a6fb0dccd43e1e06aa8dc451bdbe5512d53617 /include/dt-bindings
parentb1a1ad4b75b876ccf200f2351ae61364bf856613 (diff)
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clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
CLK_PLL_VIDEO needs to be referenced in HDMI DT entry as a possible PHY clock parent. Export it so it can be used later in DT. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/sun8i-h3-ccu.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index e139fe5c62ec..c5f7e9a70968 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
+#define CLK_PLL_VIDEO 6
+
#define CLK_PLL_PERIPH0 9
#define CLK_CPUX 14