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| author | Venkat Reddy Talla <vreddytalla@nvidia.com> | 2020-03-10 16:13:56 +0530 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-03-13 10:53:10 +0100 |
| commit | 04fac2412ba413fc9f7f792baa0b67d92ff4d1a4 (patch) | |
| tree | a37f8ea0a2c2b7388b4853c257b6b2e13219e758 /include/soc | |
| parent | 03e917b2a025d6a676af4c2ae9c410c049bda161 (diff) | |
| download | linux-stable-04fac2412ba413fc9f7f792baa0b67d92ff4d1a4.tar.gz linux-stable-04fac2412ba413fc9f7f792baa0b67d92ff4d1a4.tar.bz2 linux-stable-04fac2412ba413fc9f7f792baa0b67d92ff4d1a4.zip | |
soc/tegra: pmc: Add pins for Tegra194
Extend the Tegra194 IO pad table with additional information such as pin
names and 1.8/3.3 V settings to allow a table of voltage control pins to
generated from it. This is similar to what's done for older chips and is
needed to support high-speed modes for SDHCI where switching the pins to
1.8V or 3.3V is necessary.
Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/tegra/pmc.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h index 57e58faf660b..0dd52b0a5c1b 100644 --- a/include/soc/tegra/pmc.h +++ b/include/soc/tegra/pmc.h @@ -113,8 +113,9 @@ enum tegra_io_pad { TEGRA_IO_PAD_PEX_CLK_BIAS, TEGRA_IO_PAD_PEX_CLK1, TEGRA_IO_PAD_PEX_CLK2, - TEGRA_IO_PAD_PEX_CLK2_BIAS, TEGRA_IO_PAD_PEX_CLK3, + TEGRA_IO_PAD_PEX_CLK_2_BIAS, + TEGRA_IO_PAD_PEX_CLK_2, TEGRA_IO_PAD_PEX_CNTRL, TEGRA_IO_PAD_PEX_CTL2, TEGRA_IO_PAD_PEX_L0_RST_N, |