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| author | Marek Olšák <marek.olsak@amd.com> | 2023-01-29 23:00:59 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-02-23 17:35:58 -0500 |
| commit | b299221faf9b62166413526be2438d21257f019e (patch) | |
| tree | 82ad7566f5edbef3961d7d6177a6035ae75d6e3d /include/uapi/drm/amdgpu_drm.h | |
| parent | 4fc8fff378b2f2039f2a666d9f8c570f4e58352c (diff) | |
| download | linux-stable-b299221faf9b62166413526be2438d21257f019e.tar.gz linux-stable-b299221faf9b62166413526be2438d21257f019e.tar.bz2 linux-stable-b299221faf9b62166413526be2438d21257f019e.zip | |
drm/amdgpu: add more fields into device info, caches sizes, etc.
AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: important for conformance on gfx11
Other fields are exposed from IP discovery.
enabled_rb_pipes_mask_hi is added for future chips, currently 0.
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/drm/amdgpu_drm.h')
| -rw-r--r-- | include/uapi/drm/amdgpu_drm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 973af6d06626..b6eb90df5d05 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -715,6 +715,7 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_IDS_FLAGS_FUSION 0x1 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 #define AMDGPU_IDS_FLAGS_TMZ 0x4 +#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 @@ -1115,6 +1116,16 @@ struct drm_amdgpu_info_device { __u64 tcc_disabled_mask; __u64 min_engine_clock; __u64 min_memory_clock; + /* The following fields are only set on gfx11+, older chips set 0. */ + __u32 tcp_cache_size; /* AKA GL0, VMEM cache */ + __u32 num_sqc_per_wgp; + __u32 sqc_data_cache_size; /* AKA SMEM cache */ + __u32 sqc_inst_cache_size; + __u32 gl1c_cache_size; + __u32 gl2c_cache_size; + __u64 mall_size; /* AKA infinity cache */ + /* high 32 bits of the rb pipes mask */ + __u32 enabled_rb_pipes_mask_hi; }; struct drm_amdgpu_info_hw_ip { |